ISCAS-96 ADVANCE PROGRAM
ISCAS-96 ADVANCE PROGRAM
ISCAS-96 ADVANCE PROGRAM
(Revised May 8, 1996)
NOTE: You may wish to download this file and search it with a text editor.
NOTE: Please send any corrections to dbouldin@utk.edu
For general information and registration for ISCAS-96, click
here.
TRACK TRACK CHAIR
1. Analog Signal Processing - Edgar Sanchez-Sinencio: sanchez@sinencio.tamu.edu
2. DSP - Moncef Gabbouj: moncef@cs.tut.fi
3. Visual Signal Processing - Peter Pirsch: pirsch@tnt.uni-hannover.de
4. Nonlinear Circuits and Systems -Mani Venkatasubramanian; mani@eecs.wsu.edu
5. Power Circuits & Systems - Adrian Ioinovici: adrian@milk.cteh.ac.il
6. VLSI Systems and Applications - Eby Friedman: friedman@ee.rochester.edu
7. Neural Systems and Applications- Andreas Andreou andreou@jhu.edu
8. CAD -- Martin Wong - wong@cs.utexas.edu
ROOM ASSIGNMENTS (in general):
A--Analog; B--Neural; C--CAD; D--DSP;
E--Power; F--Nonlinear; G--VLSI; H--Visual
N--Posters for all 8 tracks
Monday:
8:30 - 10:00 Keynote Session (M1)
10:30 - 12:00 Overview Sessions(M2) (no posters)
1:30 - 3:00 Lectures/Posters (M3)
3:30 - 5:00 Lectures/Posters (M4)
Tuesday:
8:30 - 10:00 Lectures/Posters (T1)
10:30 - 12:00 Lectures/Posters (T2)
1:30 - 3:00 Lectures/Posters (T3)
3:30 - 5:00 Lectures/Posters (T4)
Wednesday:
8:30 - 10:00 Lectures/Posters (W1)
10:30 - 12:00 Panels/Posters (W2)
1:30 - 3:00 Lectures/Posters (W3)
3:30 - 5:00 Lectures/Posters (W4)
==========
ISCAS-96 Hardcopy Proceedings
Vol. I - Analog Signal Processing (13 sessions)
Power Circuits & Systems ( 4 sessions)
Vol. II - Digital Signal Processing (15 sessions)
Visual Signal Processing ( 5 sessions)
Vol. III - Nonlinear Circuits & Systems (7 sessions)
Neural Systems and Applications (9 sessions)
Vol. IV - VLSI Systems and Applications (10 sessions)
Computer-Aided Design ( 9 sessions)
==========
The following is an alphabetical author index of ISCAS-96 papers.
The paper number is coded:
M = Monday; T = Tuesday; W = Wednesday
1 = 0830-1000; 2 = 1030-1200; 3 = 1330-1500; 4 = 1530-1700
A = Room A; ... ; Room H (lectures); N = Room N (posters)
01-50 = order of presentation within the session.
AUTHOR ---------- PAPER#
Aas, E.J. W1N31
Aas, E.J. M4G01
Abdulghafour, M. T1N01
Abe, M. T2N11
Abel, A. T1N19
Abeysekera, S.S. M4N01
Abou-Allam, E. T2N05
Abouchi, N. T3N28
Aboulhamid, E.M. T2N42
Aboulnasr, T. T1D01
Abraham, J.A. T3N47
Abramovich, Y.I. W3D02
Abreu, E. W3H03
Abu-Ghalune, J.M. M3N09
Abur, A. W2N27
Aburdene, M.F. W4N11
Abusland, A. T2N35
Abusland, A. T2N36
Acha, S. W2N25
Adachi, M. M2F04
Adachi, M. T2H02
Adler, V. T1N30
Agarwal, G. T1D04
Agarwal, R. T3N07
Agathoklis, P. W4F04
Agathoklis, P. W2N08
Ahmad, M.O. W4N07
Ahmad, M.O. W2N15
Ahmadi, M. M4N18
Ahmadi, M. T4N41
Ahmed-Fekih, L. W1E03
Ahrabian, Q. T2N49
Aihara, K. T1F01
Ainspan, H.A. T1G03
Aizawa, K. T2N29
Akers, L.A. W3B01
Akers, L.A. W1B02
Akers, L.A. T1N41
Al-Dabass, D. W3N10
Al-Hashimi, B. T4N05
Al-Numay, M. W1N21
Albicki, A. T2N41
Albicki, A. W2N37
Alexander, W. T3N11
Alford, C.O. W2N34
Ali, A. T1G01
Allbutt, G. T1A03
Allen, M. T2N01
Allen, P. E. W4A04
Allen, P.E. W1A01
Allgood, D. T3N33
Alpert, C.J. W1C01
Altamirano-Gonzalez, G. W3E02
Altamirano-Gonzalez, G. W3N11
Amari, S. T2H02
Amer-Yahia, C. M4N20
Amin, M.B. T1N44
Amirazodi, J. W2N28
Amphlett, R.W. T3N09
Anderson, M. T3N15
Andre, E. M3A04
Andreou, A.G. T2N34
Andreou, A.G. W1B03
Andreou, A.G. W2G05
Andreou, A.G. M3B04
Andreou, A.G. M2B01
Angulo-Ramirez, J. W3E02
Angulo-Ramirez, J. T4E01
Antoniou, A. T4B01
Antoniou, A. W4F03
Antoniou, A. T4N12
Antoniou, A. M4N10
Antoniou, A. M3N40
Arai, H. W1H01
Arce, G.R. W3H02
Areibi T4N47
Arena, P. M4F03
Arias, A. M4N26
Arias, J. M4N26
Arik, S. T3N38
Ariyama, K. T3N13
Aronhime, P.B. T3N41
Aronhime, P.B. W2N01
Aronhime, P.B. W2N06
Aronhime, P.B. W1N05
Arslan, T. W1N36
Arslan, T. T1N09
Arthur, B.J. T3N31
Asada, K. W1H01
Asai, H. W2N40
Astola, J.T. W3D01
Athas, W.C. T1N37
Au, O. C. M3N15
Aubert, A. M3A04
Augergne, D. W4N43
Baba, T. M3N43
Babu, M. W2N21
Baccarani, G. T4D03
Baglio, S. M4F03
Bakic, P.R. W3N39
Bakker, A. W3G03
Balbuena-Ortiz, L. W1N02
Balestro, F. M3A04
Ball, C.F. W1C02
Baltes, H. W3A03
Baltes, H. W4G03
Bamberger, R. W2D04
Bampi, S. T1N45
Banerjee, P. W1C03
Barnett , R. W3N25
Barranco-Linares, B.T1N33
Barriga, A. T3B02
Bartley, N. W2N13
Baschirotto, A. W3N26
Baturone, I. T3B02
Bauer, P.H. M3N07
Bauer, P.H. T4N17
Bauer, P.H. W4D02
Bayoumi, M. M4G02
Becker, B. T4N48
Becker, B. W4N31
Becker, L. W2N34
Begovic, M. W2N31
Bellanger, M. M4D03
Belt, H.J.W. M3N12
Bendak, M. T3N14
Benedetti, A. W1N24
Benediktsson, J.A. W2N42
Benmahammed, K. T4N40
Bennour, I.E. T2N42
Berg, A.P. T4N14
Berg, A.P. W2N11
Berg, E. M4N46
Bergouignan, F. T3N28
Bermudez, J.C.M. W1D03
Bershad, N.J. W1D03
Beyene, W. T1N26
Bhattacharya, D. T4B01
Bhattacharya, D. M3N40
Bhupathi, L. W3C03
Biarge-Rodellar, V. W4B03
Biel, D. M4N27
Bilbro, G. W3N43
Billiot, G. W1N49
Biman, A. M3N05
Bisdounis, L. M4N43
Bistritz, Y. W4F01
Blalock, B.J. W1A01
Bland, D.M. W3D03
Blatner, P.J. W3N45
Boahen, K. M2B02
Boahen, K. M3B01
Boahen, K. T2N33
Boelcskei, H. W2D02
Boemo, E.I. T2N31
Boissenvain, J. T2N01
Bolchini, C. T2N45
Boluda, J.A. W3A02
Borsodi, T.P. M3N01
Bose, T. M3N13
Bouchakour, R. M3N47
Bouldin, D. T4G04
Boutillon, E. W1G04
Braiek, B.E. W2N22
Brailove, A.A. T2F03
Brattoli, M. T4N27
Brayton, R.K. T3C02
Brayton, R.K. T3C01
Bresler, Y. W3H04
Brigati, S. T3A03
Britton, C. T2N01
Brown, K. M3N42
Bruno M4N27
Bruton, L. W4N18
Bruton, L. T4N15
Bruton, L. W2N13
Bruun, E. T2N04
Bryan, W. T2N01
Brzakovic, D.P. W3N39
Bucher, M. W1N44
Bucher, M. M3N46
Bull, D.R. T3N09
Bull, D.R. M4H01
Bull, D.R. T4D04
Bull, D.R. W3N13
Bull, D.R. W4H01
Buonanno, G. T2N45
Burgess, S. K. W3N49
Burghartz, J.N. T1G03
Burrus, C.S. W2D01
Burrus, C.S. T2N12
Cabrera, S.D. T2N26
Caceres-Ceballos, J W4E02
Cahill, L.W. W4D04
Cahill, L.W. W4N24
Cai, S.S. W2N02
Cain, G.D. T2N07
Caiulo, G. M4N05
Caloba, L.P. T3N42
Calvente, J. M4E03
Calvente, J. M3E01
Campbell, D A. W4D04
Campbell, D.A. W2N44
Campbell, D.A. W4N24
Campolucci, P. W2N41
Camposano, R. T2N40
Canora, F.J. T1G03
Cantoni, A. M4N01
Cao, H. Q. W1H03
Cao, W. M4N31
Cao, X. T2H01
Cao, Y. W1B01
Cardarilli, G.C. M3G04
Cardoso, J.F. T1H04
Cardoso, J.F. T1H02
Carlosena, A. T1A01
Carlson, B.S. T3G02
Carmona, R. W1N39
Carr, F. T1G01
Carrabina, J. W3N44
Carroll, T.L. T3F03
Carvalho, N.B. T4N23
Casinovi, G. W1N43
Castellano, G. M3N41
Castello, R. W3N26
Castilla, M. M4N30
Castro-Dominguez, R. W1N39
Cathey, J.J. M3N28
Cauwenberghs, G. M4B03
Cauwenberghs, G. M3B04
Cauwenberghs, G. W3N34
Cauwenberghs, G. W4N27
Cavadini, M. M4N13
Ceyua, R. M3E01
Cha, J.J. W1G02
Chae, S.I. T4N32
Chae, S.S. W3N15
Chakrabarti, C. T4N34
Chan, P. T3N27
Chan, P. W3N42
Chan, W. W1F04
Chan, Y.H. M3N14
Chan, Y.L. W4N15
Chang, C.H. W4N34
Chang, C.H. W3N09
Chang, F.Y. W2N48
Chang, F.Y. M3N48
Chang, H. T2N02
Chang, H. W3N31
Chang, H. M4C04
Chang, S.F. M3H03
Chang, S.F. M3H04
Chang, Y.C. T2N26
Chang, Y.T. W3N09
Chang, Y.W. M3C03
Chantrapornchai, C. T4C04
Chao, L.F. W3C03
Chao, L.F. T4N49
Chao, L.F. T3C04
Charleston, S. W1D04
Chatterjee, A. M3G03
Chau, P.M. T3N14
Chau, P.M. M3N38
Chen, C. W2N39
Chen, C.I.H. M4N42
Chen, C.L. W1D01
Chen, C.P. M3C01
Chen, C.Y. W1N40
Chen, D.C. W3B04
Chen, D.L.P. M4N42
Chen, D.Z. W3N45
Chen, F. W4A01
Chen, G. M2F03
Chen, G. T3N23
Chen, G. T4F02
Chen, G. W1F02
Chen, G. W1N28
Chen, H.H. T2C03
Chen, J. M3A03
Chen, K.N. W4N45
Chen, K.N. W3N05
Chen, K.N. T4N44
Chen, L.G. W4N16
Chen, L.G. W4H03
Chen, L.G. M4N34
Chen, P.S. W4N36
Chen, R.M.M. T4N19
Chen, R.M.M. W3N47
Chen, R.M.M. M4N45
Chen, S.G. T4N35
Chen, T. T2E01
Chen, T. T2E03
Chen, T. T4N08
Chen, T. T2N13
Chen, W.K. M4N21
Chen, Y.C. W1N38
Chen, Y.L. . W3N32
Cheng, C. W1N15
Cheng, C.K. M4C01
Cheng, K.H. W1N33
Cheng, R. M4N29
Cheng, S.F. W3N30
Cheng, Y.K. T2N47
Cheng, Y.K. M3N45
Cherkauer, B.S. M4G03
Cheung, D. T3N27
Cheung, P.Y.K. T2N32
Cheung, P.Y.K. T2N39
Cheung, P.Y.K. T1N49
Chiang, C.Y. W3N32
Chiang, D. T3A04
Chiang, H.D. W1N29
Chiang, H.D. W2N26
Chiang, H.D. M3N23
Chiang, M.C. M4N34
Chickamenahalli, S.A. M3N28
Chien, C. T2N43
Chin, Y.L. T3N34
Ching, P.C. W4N19
Chioffi, E. T4N27
Chiou, L. T1N32
Chiper, D.F. W3N14
Chitrapu, P. M4N09
Chiu, S. T3C03
Chiu, Y.M. W4N16
Chiueh, T.D. W2N39
Choi, H. T2N30
Choi, J.S. M3N16
Cholewo, T.J. T3N41
Choma, J. W3N49
Chou, E.Y. W3B04
Chou, T. W3C04
Chow, M.C.W. W3N42
Chowdhury, B.H. W1N27
Choy, S.S.O. M3N14
Chren, W. W3F04
Chu, R. T1G01
Chu, Y. T1N16
Chu, Y.H. W1N33
Chu, Y.H. T3G01
Chu, Y.H. W1N34
Chua, L.O. T1B02
Chua, L.O. T2F01
Chung, E. T1N48
Chung, H. M3E04
Chung, J.J. M3H01
Chung, W.Y. T3N34
Cichocki, A. T2H02
Cichocki, A. T1F02
Cirillo, A. M4N28
Cirstea, M.N. M3N31
Clonts, L. T2N01
Coban, A. W4A04
Cochran, D. M4N15
Coelho, E.A.A. M3E02
Coelho, E.A.A. M3N26
Coelho, E.A.A. M3N30
Coffield, P. T3N12
Colli, G. W4N05
Colli, G. T4N27
Coltuc, D. T1N25
Comon, P. T1H04
Connelly, J.A. W3A01
Connelly, J.A. W2N35
Corral, C.A. T1N13
Cortelazzo, G.M. W4H04
Corzine, A.R. W1N11
Creech, G.L. M3N42
Crounse, K.R. T2F04
Crounse, K.R. T2F01
Cummings, A. T2F03
Cuomo, K. M2F01
Czerepinski, P.J. M4H01
Dabrowski, A. W4D03
Dagless, E.L. W3C02
Dagnachew, B. T4N24
Dahl, B. M4A03
Damarla, R. M4N32
Das, S. W4N39
Dasgupta, A. T4C01
Davies, A.C. W3F03
Davies, A.C. T2N23
Davis, A. M3F01
Davis, A. W2N49
Davis, A. M3N03
Dawidsiuk, A. W1N42
Dawidziuk, A. W3N36
Dawkes, H. W1N45
de Castro, M. T2F02
de Faria, S. W4N13
de Figueiredo, R.J.P. T2B03
de Figueiredo, R.J.P. W2G02
de Figueiredo, R.J.P. T1B01
de Figueiredo, R.J.P. T3N23
de Freitas, L. C. M3N30
de Freitas, L.C. M3N26
de Freitas, L.C. M3N27
de Freitas, L.C. M3E02
de Gyvez, J.P. M4N22
de Queiroz, A.C.M. T3N42
de Sousa Vieira, M. W1N18
de Vicuna, L. G. M4N30
DeBrunner, V. E T2D01
DeBrunner, V.E. T3N39
DeBrunner, V.E. W1N11
DeCaro, B. W4N25
Dehkordi, P. T4G04
Demassieux, N. W1G04
den Brinker, A.C. M3N12
Deng, T.B. W2N09
Denk, T.C. T2N44
Deprettere, E. M4F01
Derryberry, R. M4N17
Desai, M. W2N06
Deschsler T4N48
Devadas, S. M4N48
DeWeerth, S.P. T1N03
Dewilde, P.M. W4F02
Dewilde, P.M. T3N44
Dharchoudhury, A. T2N47
Di Mario, G. W3N18
Dick, C. W3F02
Dick, C. T4D01
DiClaudio, E.D. W3N18
Dierickx, B. W3A02
Dilmaghani-Akbari, R. W3N40
Ding, M. T4F01
Ding, X. W1N26
Dingankar, A. T1B04
Diorio, C. M4B01
Diorio, C. T4A04
Ditto, W.L. T4F04
Dittrich, A. W1N48
Djahanshahi, H. W4G04
Djahanshahi, H. T4N41
Djennoune, S. T1N15
Djuric, P.M. W2N31
Djuric, P.M. W3N23
Dong, G. W4B04
Doughty, D.C. T3N33
Douglas, S.C. M3D02
Dozza, D. T4D03
Drabarek, J. T1N47
Draidi, J.A. W4N09
Drechsler, R. W4N31
Drogoreanu, V. T4N22
Du, D.H.C. M4C03
Du, D.H.C. T2C04
Dubois, E. W2N46
Dumitras, A. W1N03
Dunham, J. M4N17
Edwards, C. T3N30
Edwards, R. T. W3N34
Egi, Y. T2N29
Egiazarian, K.O. W3D01
Ehsanian, M. T3E01
Ekanayake, M.M. T2N18
Eker, M. M. W3N49
El-Gamal, M. T1N01
El-Masry, E.I. T3N05
El-Masry, E.I. T2N05
El-Moudni, A. M4N20
El-Moudni, A. T1N15
Elchouemi, A. M4G02
Eldin, A.G. W3N33
Elias, P.J.H. T2C02
Emamchaie, S. T4B02
Embabi, S. T3E02
Emery, M. T2N01
Endo, T. T1N21
Endo, T. W1F01
Engel, P.M. M4N41
Enz, C. T2A03
Enz, C.C M3N46
Enz, C.C. W1N44
Enz, C.C. T2A01
Eom, K.S. T3N36
Ericson, N. T2N01
Ersoy, O.K. W2N42
Erten, G. W4B01
Esbensen T1C02
Eshraghi, A. W4N28
Eskiyerli, M.H. W1N01
Espejo, S. W1N39
Eswaran, C. W2N21
Etter, D.M. T4H04
Etzel, A. T4N45
Faccio, M. W3A03
Fairman, F.W. T2N22
Falkowski, B.J. W4N33
Falkowski, B.J. W4N34
Falkowski, B.J. W4N32
Fang, S. M3N39
Fang, W.H. T1N16
Fang, Y. T2N41
Farias, V.J. M3N26
Farias, V.J. M3N27
Farias, V.J. M3N30
Farias, V.J. M3E02
Farison, J.B. W2N17
Farrell, R.J. W4N29
Fedi, G. W4C04
Feely, O.C. W4N29
Feely, O.C. T2N19
Feichtinger, H.G. W3N22
Feichtinger, H.G. W2D02
Felderhoff, T. T4N21
Feldmann, U. T1N02
Feldmann, U. T3N21
Felici, S. W3A02
Fellman, R. T3N14
Femia, N. M4E02
Femia, N. M4N28
Feng, P. W3H04
Ferguson, P.F. T3A01
Ferguson, P.F. T3A02
Fernandez, F. W4C03
Fernandez, F.V. W4C01
Ferney M. T1N15
Ferney, M. M4N20
Fettweis. A. T4N18
Fiez, T. W4N28
Fiez, T. T3N17
Filanosky, I.M. W2N02
Filho-Noceti, S. T4N01
Fiocchi, C. M4N05
Fischer, G. M3N03
Fitzgerald, D. T2N19
Flueck, A.J. W1N29
Font, J. M3E01
Fortuna, L. W4N42
Fortuna, L. M4F03
Fossas, E. M3E01
Fournier, J.M. W1N49
Fraca, J.E. T3N04
Franca, J.E. M4D06
Franca, J.E. T4E04
Franca, J.E. W3N02
Franca, J.E. W4C02
Franca, J.E. W3N27
Franca, J.E. T3N03
Franca, J.E. M3N06
Francesconi, F. W4E03
Francis, B.A. T4N08
Francis, B.A. T2N13
Franques, V.T. T2D03
Franzon, P. W3N43
Frey, D. T4N29
Friedman E.G. M4G03
Friedman, E.G. W1G03
Friedman, E.G. T1N30
Fu, C. T3C03
Fu, K.W. W3N12
Fujii, M. M4N25
Fujii, N. T4D02
Fujii, N. T1A02
Fujii, T. T2N27
Fujita, G. W1H02
Fujita, M. T3C02
Fujiwara, H. W1H01
Fukui, Y. T1N07
Fukui, Y. T4N02
Fukunaga T1C01
Fukuyama, Y. W2N26
Furst, C.E. W4E04
Furth, P.M. W1B03
Furukawa, T. W2N18
Furukawa, T. T2N21
Gabbouj, M. T1N10
Gaddoni, M. T4D03
Gaitan, M. M2G05
Galias, Z. T1N23
Galias, Z. T1F02
Galton, I, T4N20
Galton, I. W3N28
Galton, I. T1G05
Gan, Q. W3N38
Gao, S. T2N15
Garg, H.K. W4N10
Garverick, S.L. M2G04
Garverick, S.L. T3N30
Gatti, U. M4N05
Gaudiano, P. T2F03
Ger, M. T2N03
Gerna, D. T4N27
Gesteira-Gomez, M. T2F02
Ghanbari, M. W4N13
Ghuneimi, N.M. W4N09
Gielen, G. T2N48
Gielen, G. W4C03
Gierkink, S.L.J. T3E03
Gillo-Simon, J. T2N01
Giral, R. M3E01
Girod, B. M2H01
Gockel T4N48
Goh, C.K. W1N07
Gollamudi, S. M3D04
Golob, R. W1N30
Gomariz, S. M4N26
Goncalves, R.T. T4N01
Gonzales, F. M4N22
Gonzalez, J.G. W3H02
Gonzalez-Martinez, A. W1N02
Gopinathan, V. W4N26
Gorokhov, A.Y. W3D02
Goru, V.K. W1B02
Gotarredona-Serrano, T. T1N33
Goto, K. W1H01
Gotschlich, M. T3N10
Gotz, M. T3F01
Gotz, M. T1N19
Gotze, J. W2D01
Goutis, C.E. M4N43
Graffi, S. T1N27
Gray, J. M3N32
Grebogi, C. T3F02
Green, M. M3F02
Griffin, P.J. W1N26
Grigorie, M. W3A04
Grisel, R. T3N28
Gschwind, M. T4N37
Guangrui, H. M3N39
Gubina, F. W2N29
Gubina, F. W1N30
Guglielmi, N. W1N24
Guinjoan, F. M4N26
Guinjoan, F. M4E03
Guo, J.H. W3N08
Gupta, R. T2N24
Gupta, R.K. T4C02
Gupta, R.K. W4N35
Hadidi, K. T1N04
Haeberli, A. W3A03
Hahm, M.D. W1G03
Hakkarainen, H. W4N48
Hakkinen, J. T3E04
Halonen, K. W4A02
Halonen, K. T1G02
Halonen, K. W3N36
Halonen, K. W1N42
Halonen, K. W4N04
Halonen, K. M4N02
Hamada, N. M3N11
Hamamoto, H. T2N29
Hamilton, A. M3B03
Hamilton, A. T4N04
Hammerschmied, C. W4G01
Han, G. W1B04
Han, G. T1N38
Han, S. T1N28
Hanna, M.T. W4D01
Hanna, M.T. T2N09
Hansen, F. T1N36
Hansen, K. T1G04
Hardy, L. M3N47
Haritantis, I. T4E02
Harjani, R. W3N25
Harjani, R. W4N01
Harjani, R. W3E03
Harnefors, L. W1N10
Harris, F. T4D01
Harris, J.G. M4B04
Harris, J.G. T1N39
Harris, J.G. W1N23
Harteneck, M. T3H01
Hartwig, F. T1N17
Harvatis, C. W3N43
Harvey, I. M3N36
Hasan, M.A. W1D04
Hasan, M.K W1N12
Hasegawa, A. W1F01
Hasegawa, Y. T3N20
Hashemian, R. T2D02
Hasler, P. M4B01
Hasler, P. T4A04
Hatori, M. T2N29
Hatzopoulos, A.A. T3N22
Haurie, X. W1N47
Havet, C. T4N31
Haydt, M.S. W1N22
Hayes, S. T3F02
He, Z.L. W3N12
Heineke, R. W3E03
Helfenstein, M. T3N03
Henderson, R. T4N28
Hennig, E. W1N48
Her, T.W. W1C04
Heute, U. M4N12
Higuchi, T. M3N34
Higuchi, T. T2N11
Hikawa, H. T4N38
Hill, A. M3G02
Hill, A. T1N31
Hill, D.J. W2N07
Hinamoto, T. M3N10
Hinamoto, T. W4H02
Hirata, A. W3C01
Hisakado, T. M3N25
Hiyama, T. T1E01
Hlawatsch, F. W2D02
Ho, K.L. M4H03
Hodge, A. W4B02
Hodson, R.F. T3N33
Hofer, E. T2F02
Hoisko, S. W4N48
Holman, W. T. W3E01
Holmes, P.G. M3N31
Holzmann, P.J. T3E03
Hong, H.M. T3N34
Hong, M. W1E04
Horng, J.M. W4N44
Horrocks, D.H. W1N36
Horrocks, D.H. T1N09
Horta, N.C. W4C02
Hou, C.J. M3N04
Hovin, M. T2N36
Hovin, M. T2N35
Hsia, Y.C. W1N37
Hsieh, C.C. T2N02
Hsieh, C.T. W2N30
Hsing, R.T. M2H02
Hsu, Y. M4C03
Hu, J.D. W4N41
Hu, S.G. W4N41
Hu, X. T3N02
Hu, X. W3N45
Hu, Z. W3N10
Hu, Z. M4N29
Huang T1C01
Huang, C.L. T1E04
Huang, C.L. W2N30
Huang, C.Y. W1N40
Huang, C.Y. T1N40
Huang, H.Y. T3G01
Huang, H.Y. W1N33
Huang, H.Y. W1N34
Huang, L.Y. W2N32
Huang, M.H. T1N16
Huang, Q. M4N04
Huang, Q. W3G04
Huang, Q. W4G01
Huang, R. M4N03
Huang, R. T3N06
Huang, S.C. T4N25
Huang, S.J. W2N30
Huang, S.J. M3N17
Huang, T.C. W2N34
Huang, T.S. M3E03
Huang, X. M4N29
Huang, Y. T3A02
Huang, Y. T3A01
Huang, Y.C. T1E04
Huang, Y.F. M3D04
Hudson, R.E. T2N15
Huertas, J. T3B02
Huertas, J.L. T1N33
Hughes, J.B. T3N01
Huigsing, J.H. W3G03
Hull, C. T1G01
Hummels, D.M. T2N28
Hung, C.C. M3N17
Hurst, P. M4N06
Huttunen, H. T1N11
Hwang, C. W1N06
Hwang, S.A. W4N36
Hwang, S.H. T2N30
Hwang, Y.T. W1N35
Hyun, J.I. W1G02
Hyun, J.S. T2A04
Ibbini, M. W2N20
Iimuro, S. T3N08
Ikehara, M. T4N07
Ikehara, M. T2N14
Ikehara, M. T4N09
Imtiaz, M. M4N16
Imtiaz, M. T3H02
Inouye, Y. T2H04
Ioinovici, A. M3N29
Ioinovici, A. M3E04
Irons, F.H. T2N28
Ishida, M. T4N02
Ishida, Y. T1N21
Ismail, M. T4N26
Ismail, M. W1N06
Ismail, M. W2G07
Ismail, M. M4N47
Ismail, M. W2N05
Isoaho, J. W4N48
Itani, N. W1N04
Itoh, Y. T1N07
Ives, R.W. W2N12
Jacak, B. T2N01
Jamali, M.M. W3N33
Janik, K. M4N33
Jankowski, S. T2B04
Jantarang, S. T1N05
Jantzi, S.A. T4A01
Jarske, P. M4A02
Jelloul, M. M3N47
Jen, S.H. M3N49
Jendges, R. T3N43
Jenkins, K.A. T1G03
Jenkins, T. M3N42
Jenkins, W.K. W2N14
Jenkins, W.K. T2N16
Jensen, H.T. W3N28
Jensen, H.T. T4N20
Jensen, H.T. T1G05
Ji, W. W1E01
Jia, X.D. T4N19
Jiang, Z. M4H02
Jih, F.W. T2N02
Jin'no, K. T3N37
Jomain, L. T3N28
Jongan, P. W2N50
Joo, K.S. M3N13
Jorgensen, I.H.H. W3N24
Joseph, E. T2N03
Jou, I.C. T3B03
Jou, J.M. W3N32
Jourdain, M. M3N47
Juan, J. M4B04
Jullien, G.A. W4G04
Jullien, G.A. T4B02
Jullien, G.A. T4N41
Jumeau-Jean, R. M3N23
Jye-Shyh, F.J. T3B03
Kachab, N.I. W1A03
Kahng, A.B. T1C01
Kahng, A.B. W1C01
Kahng, A.B. T4G03
Kahng, A.B. T4G02
Kajihara, S. T3N48
Kalayjian, K. . T2N34
Kalsaggelos, A.K. M3H02
Kamata, H. T1N21
Kaminska, B. T3E01
Kang, I. W1G01
Kang, I. W1G02
Kang, S.M. T2N47
Kang, S.M. M3G02
Kang, S.M. M3N37
Kang, S.M. M3N45
Kang, S.M. T1N31
Kao, Y.L. T3N34
Kapustinsky, J. T2N01
Kar, B.K. T2N03
Karam, L.J. W1N08
Karam, L.J. T2N07
Karino, S. W4H02
Karlsson, M. T2D04
Karri , R. T4C01
Karsilayan, A.I. T4N03
Kasprzak, W. T2H02
Katsaggelos, A.K. M4H04
Kawaguchi, T. M3N43
Kawahito, S. W3G02
Kawakami, H. W2N24
Kawamata, M. T2N11
Kawata, J. T3N24
Kazimierczuk, M.K. M4E01
Kelber, K. T3F01
Kennedy, E. T2N01
Kennedy, M.P. T1N23
Kenney, J. T3H03
Kershaw, S. T3N15
Khasawneh, M.A. W4N09
Khasawneh, M.A. M3N09
Khoei, A. T1N04
Khoo, I.H. T2N17
Khoo, K.Y. W1D01
Kihara, H. T1E01
Kilias, T. T3F01
Kim, B. T1N28
Kim, C. T1N28
Kim, H.G. T4N33
Kim, H.G. T1N48
Kim, J. T2C04
Kim, J. M4C03
Kim, J.M. T4N32
Kim, J.S. W1G02
Kim, K.S. W1G02
Kim, S. W1H04
Kim, S. T1N28
Kim, Y. T2E01
Kim, Y. T2E03
Kimoto, M. T2N21
Kimura, J. W1H01
King, G. W3N10
Kinoshita, K. T3N48
Kitano, H. M3N35
Kitano, Y. W2N18
Kiya, H. W4N47
Klumperink, E.A.M. T3N29
Kneip, J. W2N33
Knol T1C03
Ko, H. T3N11
Kobayashi, T. R. W1H01
Kocarev, L. T1N22
Koch,C. M3N18
Koczy-Varkonyi, A.R. W3D04
Kogon, S.M. W3N20
Koide, T. M3C04
Koivisto, P. T1N11
Kok, C.W. W1N16
Koli, K. T1G02
Koli, K. W4N04
Konczykowska, A. W3N46
Konda, M. T3N32
Kong, J. T1N48
Kornegay, K. T1N32
Korompis, D. . T2N15
Kostamovaara, J. T3E04
Kostamovaara, J. W4N23
Kotani, K. T3G04
Koufopaviou, O. M4N43
Koullias, I. T1G01
Kozek, W. W3N22
Kozick, R.Z. W4N11
Kozlov, A.K. M3N21
Kramer, J. M3N18
Kreuzer, W. T3N10
Krummenacher, F. W1N44
Krummenacher, F. W3A04
Ku, C.W. W4N16
Kuang, S.R. W3N32
Kudumakis, P.E. M4N07
Kuh, A. T2B01
Kuh, E. T1C02
Kuhn, W.B. W2N03
Kukimoto, Y. T3C02
Kulach, C. W2N13
Kumar, N. M3B04
Kunieda, H. W2N47
Kuo, C.J. M3N04
Kuo, S.Y. T1D02
Kuo, T. M3A03
Kuo, T. W3N05
Kuosmanen, P. T1N11
Kuratli, C. W3G04
Kuribayashi, K. W3N48
Kuroda, N. W4H02
Kurosawa, K. T4N11
Kutuk, H. M3N37
Kwatra, S.C. W3N33
Kwon, Y.M. T4N33
Laakso, T.I. W3D03
Laberteaux, K. T3H03
Lacroix, A. T1N17
Lai, H.C. T3N34
Lai, Y.K. M4N34
Lai, Y.T. W4N45
Lakamsani, P. W3N16
Lallement, C. W1N44
Lallement, C. M3N46
Lam, K.N. M4N48
Lam, K.P. T1N42
Lande, T.S. T1N06
Lande, T.S. T2N36
Lande, T.S. T2N35
Langevin, M. T2N40
Larsen, F. T4N30
Larsen, F. M4A01
Larsen, F. W2N05
Larsen, F. T4N26
Lata, Z.J. W1N05
Lau, J. T3N27
Layos, M.C. T4E02
Lazarescu, V. W1N03
Lee, K.T. T3N47
Lee, C. H. W3N49
Lee, C.Y. W2N36
Lee, H. M4N46
Lee, J. T2C04
Lee, M. T4G01
Lee, M. T1N34
Lee, R. M3N42
Lee, S. W3N05
Lee, S. T1N48
Lee, T. M4C04
Lee, Y.H. T3D02
Lee, Y.P. W4N16
Lee, Y.S. M4E04
Leenaerts, D. M3F04
Leme-Azeredo, C. M3N06
Lemonds, C. W3N07
Lesniak, C M3N42
Leung, C.Y. T3N34
Leung, W.H. W2N48
Levi, A.F.J. T2G01
Lewandowsky, S. T3N39
Lewis, M. T3N12
Li , C.K. W1N14
Li , H. T4N34
Li, C.C. T4N35
Li, C.C. W4N40
Li, C.S. W2G06
Li, D. T2A02
Li, H. T4E03
Li, H.T. W3N23
Li, J. W4N35
Li, M. M4N44
Li, S.C. T3N39
Li, W. W1H03
Li, X. M4H02
Li, Y. W1N09
Liang, Y.C. W3N19
Liberali, V. W4G02
Lichtenberg, A. J. W1N18
Lieberman, M.A. W1N18
Lienig, J. T1C04
Lillis, J. M4C01
Lim, I.T. W4N21
Lim, Y.C. W1N07
Lim, Y.C. T2N10
Limbourg, I. M3N47
Lin, B.R. M3E03
Lin, F.H. W4N14
Lin, H. T4A03
Lin, H.D. W2G03
Lin, T.T.Y. M4C01
Lin, Y. T1D03
Linares, I. W3H01
Lindfors, S. W4A02
Lindfors, S. M4N02
Linsay, P.S. T2F03
Liou, M. L T2H01
Liou, M.L. W2G01
Liou, M.L. W3N12
Liou, M.L. W3N16
Liu, B. T2N10
Liu, B.D. W1N40
Liu, B.D. T1N40
Liu, C.C. W1E04
Liu, C.T. . M3N04
Liu, D.Z. T2N06
Liu, E. T1E05
Liu, K.J.R. W1N32
Liu, R.W. T2H03
Liu, R.W. T1H01
Liu, R.W. W4B04
Liu, R.Y. T3B03
Liu, S.C. W1N32
Liu, S.I. W3E04
Liu, S.L. W1A02
Liu, Y. W1N26
Liu, Y.C. W4H03
Llopisl, R.P. W3N44
Lo, K.C. T1N14
Lo, N.R. M4N46
Lopez-Buedo, S. T2N31
Lopez-Lobato, F. T3B01
Lorenzelli, F. T2N15
Lou, J. W4F03
Lou, W. T2D01
Lozowski, A. T2B04
Lozowski, A. T3N40
Lu, S.K. T1D02
Lu, S.L. M4N33
Lu, W.S. W4F03
Lu, W.S. T4N12
Lu, W.S. T3D03
Lucchese, L. W4H04
Luchetta, A. W4C04
Luk, W. S. T2C01
Luo, H. T2H03
Lyon, R.F. M3B02
Lyon, R.F. M4B02
Ma, W.C. W1N27
Machado, G. A. S. M4N49
Madadi, H. T2N49
Madhavan, B. T2G01
Madrigal, M. W2N25
Madureira, R.C. T4N23
Magotra, N. W2N12
Magotra, N. T4H03
Magrath, A.J. T3N16
Maischberger, O. T4N37
Majumdar, M. T2E04
Malcovati, P. W3A03
Malinowski, A. T3N41
Malki, H.A. W1N28
Malo, E. W4N23
Maloberti, F. W4E03
Maloberti, F. T3A03
Maloberti, F. W3A03
Maloberti, F. W4G02
Maloberti, F. M4N05
Mandyam, G. W2N12
Mandyam, G. T4H03
Manetakis, K. W4N02
Manetti, S. W4C04
Manganaro, G. M4F03
Mange, D. M3N33
Manku, T. T3N05
Manku, T. T2N05
Manolakis, D.G. W3N20
Mantri, R. M4F04
Marakhovsky, V.B. T2G02
Marienborg, J. T2N35
Marino, I.P. T2F02
Marinov, C.A. M4N24
Marionnet, F. T3N28
Marpinard, J.C. M4N27
Marqua-Alvarez, A. W4B03
Martholev, B. W1B01
Martin, D. W3N46
Martin, F. W3N13
Martin, K.W. T3N02
Martin, K.W. T3N26
Martin, K.W. T4A01
Martin, R. M4N15
Martinez, L.. . M4N27
Martinez, L. M3E01
Martinez, L. M4E03
Martinez-Silva, J. W4N06
Martinez-Silva, J. W4E01
Martinez-Silva, J. T3B01
MasÕud, A.F. W2N47
Masetti, G. T1N27
Mason, A. W3G01
Massarini, A. M4E01
Mathew, B. W4N46
Mathieu, Y. T4N31
Matsumura, K. W1H02
Matsuo, M. M4N25
Matsuyama, K. T2N14
Mattausch-Miura, M. T1N02
Mattisson, S. W1B01
Matumoto, K. W1H01
Maundy, B.J. W2N01
Maundy, B.J. W1N05
Mayes, D.J. M3B03
McClellan, J.H. W1N08
McClellan, J.H. T2N07
McGee, B. T2G03
Mead, C.A. T3N31
Mead, C.A. T4A04
Mead, C.A. M3B02
Mead, C.A. M4B02
Mead, C.A. M4B01
Meador, J.L. W3B03
Meana-Perez, H. W1N02
Mees, A. M2F02
Meguro, M. M3D03
Mehregany, M. M2G04
Mellott, J.D. T3N12
Melton, R.W. W2N34
Memon, N. T4H02
Mendil, B. T4N40
Meneses, J.M. T2N31
Meng, J. M3H04
Menolfi, C. W4G01
Menon, P.R. T2E02
Mensink, C.H.J. T3N29
Mersereau, R.M. W4N14
Mersereau, R.M. W1N17
Mersereau, R.M. W3H01
Messerschmitt, D.G. M3H03
Michalski, Z. T3N45
Michel, A.N. T1B03
Mikhael, W.B. T4N14
Mikhael, W.B. W2N10
Mikhael, W.B. W2N11
Mikhael, W.B. T4H01
Miki, T. W3B02
Milanovic, V. M3N20
Milford, D. W3C02
Miller, D.A. T3N40
Miller, J. T2N37
Miller, W.C. T4B02
Miller, W.C. W4G04
Miller, W.C. T4N41
Milor, L. M4N44
Minch, B.A M4B01
Minch, B.A. T4A04
Mirabbasi, S. T2N13
Mirzai, B. W2N23
Mitra, S.K. M4D01
Mitra, S.K. W3H03
Mitra, S.K. W3N27
Mitsubori, K. W1N20
Mitsubori, K. T1N24
Miyauchi, H. T1E01
Miyazaki, H. T3N08
Mlynski, D.A. T4N43
Mlynski, D.A. W1C02
Moen, S.D. M4A03
Moheimani Reza, S.O. T4B04
Moiola, J.L. W1F02
Molchanov, A.P. W4D02
Moldovan, L. T4E03
Molina, P.A. T2N32
Monaco, J. W4N17
Montalvo, L. M4N36
Montecchi, F. W4N05
Montecchi, F. W3N26
Monti, A. M4N23
Monti, C. W4H04
Montoro-Galup, C. T4N01
Moraes, F. W4N43
Morche, D. M3A04
Moreau, Y. T3N19
Mori, H. W1N25
Mori, H. T1E06
Mori, S. M4N25
Mori, S. M3N24
Morita, K. M4N19
Morley, D. M3N31
Moro, S. M3N24
Moschytz, G.S. T3N03
Moschytz, G.S. W2N23
Moschytz, G.S. T4N13
Moschytz, G.S. T2N17
Moshnyaga, V.G. T2N44
Mossberg, K. W1N10
Motamed, A. W1N06
Motamed, M. W4A03
Moulding, K.W. T3N01
Mourad, S. W1N22
Mu, D.C. M4N21
Mucha, I. W4N30
Muddu, S. T4G03
Muddu, S. T4G02
Muller, P. M2B03
Muneyasu, M. M3N10
Munuzuri, A.P T2F02
Munuzuri-Perez, V. T2F02
Murgu, A. W4N38
Murphy, C.A. T1N23
Murray, A.F. M3B03
Muscato, G. W4N42
Musil, V. W1N46
Musrock, M. T2N01
Nachbar, P. T2B02
Naess, S. T1N06
Nagai, N. W1H01
Nagai, T. T4N07
Nagai, T. T4N09
Nagari, A. W3N26
Nagy, M. T3N30
Naim, D.G. T1A03
Nairn, D.G. M3N05
Najafi, K. W3G01
Najim, M. T1N12
Nakachi, T. M3N11
Nakagawa, S. W1F03
Nakajima, K. W1N32
Nakamura, T. T3N37
Nakanishi, I T1N07
Nakanishi, Y. W2N26
Nakatomi, T. W1H01
Nakayama, T. W2N40
Narasimhamurthi, N. M4N18
Narathong, S. W4N25
Nauta, B. T3N29
Navas, R. T3B04
Neeley, J.E. W1N23
Nemouchi, Y. T4N31
Neves, R. W3N27
Newcomb, R.W. T2B03
Newcomb, R.W. W4B02
Ng, C.S. W1N07
Ng, H.S. T1N42
Ng, S.W. M4E04
Nguyen, H.T. M3G03
Nguyen, T.G. W1N16
Ni, J.Q. M4H03
Nijim, Y.W. T4H01
Nikolaidis, S. M4N43
Ninomiya, H. W2N40
Nishi, T. M3F03
Nishihara, A. T3N08
Nishihara, A. T4D02
Nishio, Y. T2N20
Nishio, Y. T3N24
Nishio, Y. W1N41
Nishio, Y. T1F03
Nishitani, T. M4D02
Nishitani, T. W2G04
Nix, A. T4D04
Njoelstad, T. M4G01
Noguchi, Y. M3H03
Nogueras, A. T1G04
Nomure, M. T2N27
Norsworthy, S. R. M3A02
Nossek, J.A. T2B02
Nossek, J.A. M4N35
Nourani, M. M4C02
Nowacka, E.B. T3N44
Nowrouzian, B. M3N01
Numata, H. W3N41
Nys, O. T4A02
O'Keefe, J.M. W4N24
O'Shana, O. W4N03
Odegard, J.E. W2D01
Odegard, J.E. T2N12
Ogborn, L. M3N22
Ogorzalek, M.J. M2F04
Ogorzalek, M.J. T1N23
Ogorzalek, M.J. T1F02
Ogunfunmi, T. W3N35
Oh, H. W4B01
Oh, H.J. T3D02
Oh, J. M3C02
Oh, W.J. T3D02
Oh, Y. W2N17
Ohmacht, M. W2N33
Ohmi, T. T3N32
Ohmi, T. T3N35
Ohmi, T. T3G04
Ohtsuka, T. W2N47
Oishi, S. W1N18
Okada, K. T4N46
Okada, Y. W1H01
Okuda, M. T2N14
Okumura, K. M3N25
Olejniczak, K.J. W2N28
Olgaard, C. T4N06
Oliveira, J. T3N04
Oliveira, R.C. M3N30
Olurotimi, O. W4N39
Ong, S. W3N31
Ono, S. T2N27
Onodera, H. W3C01
Onodera, H. T4N46
Onofri, G. T1N27
Onoye, T. W1H02
Ootubo, H. W1H01
Opal, A. W2N45
Oralkan, O. T4N03
Orchard, M. W2H01
Ordinas, J. M4N30
Orlandi, G. W3N18
Ortmeyer, T. T1E01
Oshima, Y. M3N49
Ota, Y. T2N38
Ottaviani, D. T1N12
Ozdemir, E. W1N36
Paakkonen, M. T1G02
Paasio, A. W3N36
Paasio, A. W1N42
Pache, D. W1N49
Pal, B.C. W1E02
Palara, S. T1N27
Paliouras, V. T4N36
Pan, S.B. W3N15
Panovski, L. . T1N22
Panusopone, K. W1N13
Papachristou, C. M4C02
Papachristou, C. T3C03
Papamichalis, P. M4D04
Papantonopoulos, I.N. T2N28
Papathanasiou, K. T4N04
Pappas, M. M3D01
Parameswaran, A. M2G02
Pardo, F W3A02
Parhi, K.K. M4D05
Parhi, K.K. T2E04
Parhi, K.K. W1N09
Parhi, K.K. W4N20
Parhi, K.K. T2N44
Parhi, K.K. M4N36
Park, D. T4C03
Park, D.J. T3N36
Park, H. T1N28
Park, H. T1N28
Park, R.H. W3N15
Parlitz, U. T1N22
Pasero, E M4N40
Pasotti, M. T4N27
Pastore, S. W1N19
Patterson, E.B. M3N31
Paul, B. M3N42
Paul, O. W3A03
Paulino, N. T4E04
Payne, A.J. W1N01
Payne, A.J. M4A04
Payne, R. S. M2G03
Pedram, M. M3C02
Pedro, J.C. T4N23
Pei , S.C. T2N08
Pei, S.C. W1N15
Pei, S.C. W4N08
Pentland, A. W2H03
Pereira, A.A M3N26
Perez, J.J. W3A02
Perkowski, M.A. W4N03
Perry, R. T4D04
Petajan, E. W2H04
Petersen, I.R. T4B04
Petkov, G.P. T2N23
Petraglia, A. W3N01
Petraglia, A. W3N27
Petraglia, M.R. W1D02
Petrie, C.S. W2N35
Petropulu, A.P. M4N08
Pham, C.K. T1N18
Pham, C.K. W2N04
Phoong, S.M. W2D03
Piazza, F. W2N41
Piccirilli, M.C. W4C04
Pierzchala, E. W4N03
Pihl, J. W1N31
Pileggi, L. T2N24
Pillai, S.R. M4N10
Pillai, S.R. M3N40
Pimchaiping, N. T2B03
Pirsch, P. W2N33
Pister, K.S.J. M2G01
Pister, K.S.J. M4N46
Pitas, I. M3D01
Piuri, V. M4N39
Plasil, F. T2N01
Ploeger, P. T2N40
Plotkin, E.I. T3N07
Pomeranz, I. T3N48
Pookaiyaudom, S. T1N05
Popov, A. M4A02
Porra, V. T1G02
Porra, V. W3N36
Porra, V. W1N42
Povazanec, J. W1N46
Poveda, A. M4E03
Powell, T. T4G04
Premaratne, K. T2N18
Premaratne, K. T4N17
Premoli, A. W1N19
Prigge, O. T1N02
Principe, J.C. M4B04
Privitera, G. T1N27
Provine, J. W4N18
Przybyszewshi, A. T2F03
Pu, C. T1N39
Pudelko T4N48
Pun, K.P. M3N48
Punzenberger, M. T2A03
Purushotham, A. T3N30
Purvis, A. T1N14
Pyo, I. M3C02
Quakkelaar, S. M4N46
Raghupathy, A. W1N32
Rahardja, S. W4N32
Rahardja, S. W4N33
Rahkonen, T. W4N12
Rahkonen, T. W4N23
Rahkonen, T. T3E04
Rajan, P.K. T4N16
Ramaswamy, A. W2N10
Ramirez-Angulo, J. W3N11
Rao, K.R. W1N13
Reber, M. T1N35
Reddy, H.C. T2N17
Reddy, H.C. T4N16
Reddy, S. T3N48
Redmill, D.W. W4H01
Reekie, H.M. M3B03
Reider, P. W2D01
Reis, R. W4N43
Reiszig, G. T3N21
Reljin, B.D. W3N39
Restituto-Delgado, M. T3F04
Restituto-Delgadol, M. W4E02
Rezania, S. T3N26
Riad-Elshabini, A. W2N03
Ribas, L.I. W3N44
Rich, D. A. M3A02
Rieder, P. M4N35
Riera, J. W3N44
Ritoniemi, T. T3N18
Robert, M. W4N43
Roberts, G.W. M3A01
Roberts, G.W. W1N47
Robilliart, E. W2N46
Rocha, D. M3N06
Rodrigues, A.P.R. W1D02
Rodriguez-Artes, A. W4N37
Rohrkemper, R. T2N03
Rohrs, C. T3H03
Rosenbaum, E. T2N47
Rosenbaum, E. M3N45
Rosenberg, J.J. T4N20
Rossi, M. T3N25
Roy, K. W3C04
Rueda, A. M3N02
Ryu, S. W3N31
Saab, D.G. W4N46
Saarinen, K. T1N10
Saberi, A. M4F04
Sadjadi-Azimi, M.R. W1D04
Safari, R. M4N18
Saito, A. W2N09
Saito, R. W1H01
Saito, T. T3N37
Saito, T. W4N49
Saito, T. W1F03
Saito, T. W1N20
Sakaguchi, T. W1H01
Salam, F. W4B01
Salama, C.A.T. T1N36
Salapura, V. T4N37
Salice, F. T3N49
Salmeri, M. M3G04
Salsano, A. M3G04
Sandage, R.W. W3A01
Sandberg, I.W. T1B04
Sanders, S. W4A03
Sandler, M.B. T3N15
Sandler, M.B. T3N16
Sandler, M.B. M3N41
Sandler, M.B. M4N07
Sano, B. T2G01
Sansen, W. T2N48
Sansen, W. W4C03
Santos, P. W3N02
Sapatnekar, S.S. T1N46
Saquer-AL, A.A. W1A03
Saraiva, J.T. T1E03
Sarajedini, A. M3N38
Saramaki, T. T3N18
Saramaki, T. W4N22
Sarpeshkar, R. M4B02
Sarpeshkar, R. M3B02
Sarpeshkar, R. M3N18
Sarrafzadeh T1C03
Sassene, D.H. T4N06
Sato, M. W1H01
Satoh, K. T3N13
Saunders, C. W4N25
Savignac, D. T1N02
Savkin, A.V. T4B04
Sawabe, T. T2N27
Sayed, S. M4G02
Scharinger, J. W3N22
Schaumann, R. T3A04
Scheffer, D. W3A02
Schimpfle, C. M4N35
Schindler, V. T2G04
Schmitz, C.D. T2N16
Schneider, M.C. T4N01
Schobinger, M. W3N17
Schreier, T. T4A03
Schuler, A.J. T2B02
Schuster, G.M. M4H04
Schutt-Aine, J. T1N26
Schwarz, W. T1N19
Schweizer, J. T1N20
Sciuto, D. T2N45
Sclabassi, R.J. W4N40
Sculley, S. T3N17
Sculley, T. W1N04
Sedra, A.S. T4A01
Senn, P. M3A04
Senn, P. W1N49
Serafat, M.R. M4N12
Serrano, L. T1A01
Serrano-Gonzalez, F. W4N37
Setti, G. T2F04
Settineri, R. T1N12
Sha, E.H.M. T4C04
Shah, P. W3N06
Shalash, A. W4N20
Shalfeev, V.D. M3N21
Shama-Abu, E. M4G02
Shanbhag, N.R. M3G01
Shao, J.H. W3N47
Shaw, A.K. T3H02
Shaw, A.K. M4N16
Shaykh-Al, O.K W1N17
Shen, T. T1N49
Shen, Y. M4N45
Shetty, D.H. W3N33
Sheu, B.J. M3N49
Sheu, B.J. W3B04
Sheu, M.H. W4N44
Sheu, M.H. W3N30
Shi, B. T1B02
Shi, B.E. W3N37
Shi, J..F. T3C04
Shi, W. M4N29
Shi, Y.Q. M3N19
Shibata, T. T3G04
Shibata, T. T3N32
Shibata, T. T3N35
Shieh, M.D. W4N44
Shieh, M.D. W3N30
Shin, H. T4C03
Shinoda, K. M4N25
Shiple, T. T3C01
Shirakawa, I. W1H02
Shiue, M.T. W2N32
Shoaei, O. W1A04
Shono, K. W2N04
Shridhar, M. M4N18
Shu, H. T4N08
Sidiropoulos, N.D. T3D01
Signell, S. W1N10
Siilasto, S. T1G02
Sijercic, Z. T1D04
Silva, J.B. T4A03
Simon, J. M4N46
Simon, S. M4N35
Simonelli, O. M3G04
Simpson, M. T2N01
Simula, O. M4N38
Sin, T.P. T2N02
Sinencio-Sanchez, E. W1B04
Sinencio-Sanchez, E. W1N02
Sinencio-Sanchez, E. T3E02
Sinencio-Sanchez, E. W2N19
Sinencio-Sanchez, E. T3B01
Sinencio-Sanchez, E. T1N38
Singhal, V. T3C01
Siu, W.C. W1N14
Siu, W.C. W4N15
Siu, W.C. M3N14
Sloan, A. W2H02
Smadi-Al, A. W3N21
Smith, M. W4N17
Smith, M. W3H01
Smith, R. T2N01
Smith-Martinez, A. T2G03
Snelgrove, W.M. T3D04
Snelgrove, W.M. W1A04
So, H.C. W4N19
Solano-Sanchez, S. T3B02
Soli, S.F. T2N15
Sommer, R. W1N48
Song, H.K. M3N16
Song, L. T1N10
Song, M. W3N03
Soni, R. W2N14
Soong, B.H. W3N19
Sousa, J.T. T1N49
Soyuer, M. T1G03
Speciale, N. T1N27
Spence, R. W1N45
Spencer, N.K. W3D02
Sridhar, R. T2G03
Sriranganathan, S. W4H01
Stearns, S.D. T4H01
Steenaart, W. T3N25
Stefanelli, R. T2N45
Steigerwald, L. T4N29
Steiner, P. M4F02
Stephenson, F.W. W2N03
Stewart, R.W. T3H01
Stojanovski, T.K. T1N22
Stouraitis, T. T4N36
Straub, S. M4N37
Strmcnik , B. W2N29
Stroud, C. M4N32
Strzeszewski, B. T1N43
Stubberud, A.R. T2N17
Stubberud, P.A. T4N13
Su, C. W2N32
Su, H. W1N45
Su, H. M4N47
Su, W.J. M4N21
Sucher, R. T1N08
Sue, C.L. W1N35
Suetsugu, T. M4N25
Sugino, N. T3N08
Sullivan, J. T2N01
Summerfield, S. T3N15
Sun, M. W4N40
Sun, M. T4H03
Sun, T.P. T3N34
Sundararajan, D. W4N07
Sung, W. W1H04
Sunwoo, M.H. W3N31
Suriano, M.A. T2N26
Surti, P. T4N49
Suyama, K. M3N44
Suyama, K. W4N26
Suzuki, T. M3C04
Sveinsson, J.R. W2N42
Sveinsson, J.R. T2N22
Svensson, C. T1N29
Svensson, L.J. T1N37
Swain, P.H. W2N42
Swamy, M.N.S. T3N07
Swamy, M.N.S. W2N15
Szczupak, J. W1D02
Tabatabai, A. W2H06
Tachiki, M. M4N46
Tadokoro, K.Y. W3G02
Taguchi, A. M3D03
Tahernezhadi, M. T3H04
Takagi, S. T1A02
Takatsu, M. W1H02
Tamaru, K. T2N44
Tamaru, K. T4N46
Tamaru, K.. W3C01
Tamayo-Moreira, O. M4N22
Tan, M.A. T4N03
Tan, S. M4F01
Tanaka, H. A. W1N18
Tanaka, K. T4F03
Tanaka, M. W3N41
Tanaka, M. W2N04
Tang, P.S. W3N04
Tanji, Y. T2N20
Tarczynski, A. W3D03
Tavsanoglu, V. T3N38
Tavsanoglu, V. W2N16
Taylor, D.G. W1N21
Taylor, F.J. T3N12
Taylor, J. W3N40
Tchamov, N. M4A02
Tekmen, Y. W3N43
Tekumalla, R. T2E02
Tellez T1C03
Temes, G.C. W4N27
Temes, G.C. T3A01
Temes, G.C. T3A02
Teng, C.C. T2N47
Teng, C.C. M3G02
Tenor, J. M4N27
Thaler, M. M4N13
Tham, J. L. T1G01
Thelen, D.C. W3N29
Theogarajan, L. W3B01
Theogarajan, L. T1N41
Thiele, L. W3N17
Thiran, P T2F04
Thompson, A. M3N36
Thomsen, S. W2N37
Thripuraneni, J. T2D01
Tian, X. T2B01
Tiiliharju, E. W4N04
Tiiliharju, E. T1G02
Titlebaum, E.L. W1G03
To, H.Y. M4N47
Tofano Jr., R. M3N27
Tolonen, P. T1G02
Tomasini, A. T4N27
Tomsovic, K. T1E02
Tong, L. T1H03
Tong, S. W2N38
Tongsima, S. T4C04
Tonietto, D. W4G02
Toole, W. T3N05
Torelli, G. T3A03
Torres, L. W4N43
Toshimichi, S. T1N24
Toumazou, C. T1A04
Toumazou, C. W1N01
Toumazou, C. W4N02
Toumazou, C. M4A04
Toumazou, C. M4N49
Towne, D.A. T4N20
Toyoshima, H. T3N13
Treviso, C.H. M3N27
Troester, G. M4N13
Tsay, J.H. W3E04
Tse, C.K. W1F04
Tse, C.K. W3N04
Tse, K.W. M4H03
Tseng, C.C. T2N08
Tsividis, Y. T2A02
Tsubone, T. W1N20
Tsui, F.C. W4N40
Tsuiki, S. T4N02
Tsukisaka, M. T2G02
Tsukutani, T. T4N02
Tsutsui, S. T4N07
Tucci, V. M4E02
Tufan, E. W2N16
Tull, D.L. M3H02
Tunheim, S.A.T. W3N24
Tuqan, J. W3F01
Tutunji , T.A. W1N11
Tweedie, L. W1N45
Tzartzanis, N. T1N37
Uchida, T. W4N47
Uebel, L.F. T1N45
Ueta, T. W2N24
Uncini, A. W2N41
Ushida, A. T1F03
Ushida, A. T3N24
Ushida, A. W1N41
Ushida, A. T2N20
Vaidyanathan, P.P. T1D03
Vaidyanathan, P.P. W3F01
Vaidyanathan, P.P. W2D03
Valsa, J. T3N46
van der Meijs, N.P. T2C02
Van Halen, P. W4N03
Van Vleck, E.S. T1F04
Vandewalle, J. T3N19
Vandewalle, J. M4F01
VanHecke, H. T2N01
Vannelli T4N47
Varghese, J.G. W1A03
Varma, S. W4N26
Varrientos , J. E. W2N19
Varshavsky, V.I. T2G02
Vazguez-Rodriguez, A. T3F04
Vazquez-Rodriguez, A. T3B04
Vazquez-Rodriguez, A. W1N39
Vazquez-Rodriguez, A. W4C01
Vazquez-Rodriguez, A. W4C03
Vazquez-Rodriguez, A. W4E02
Vega-Pineda, J. T2N26
Veillette, B. R. M3A01
Velasco, A.J. W3N44
Vemuru, S.R. T3G03
Venkatasubramanian, V. M4F04
Venkatasubramanian, V. W1E01
Verdu-Vidal, F. T3B04
Verma, V. T2N43
Veselinovic, P. M3F04
Vesma, J. W4N22
Vidal, A. W4N37
Vieira Jr, J. B. M3N30
Vieira Jr, J.B. M3E02
Vieira Jr. J.B. M3N27
Vieira Jr., J.B. M3N26
Vihavainen, K. W4N48
Vilda-Gomez, P. W4B03
Vilela, M.S. M3E02
Villalva, V.M. T2N26
Villar-Perez, V. T2F02
Vincentelli-Sagiovanni, A. T3C01
Vinnakota, B. T1N44
Viswanathan, T. R. M3A02
Vital, J. T3N04
Vizireanu, D. T4N22
Vlach, J. T3N45
Vlach, J. W4A01
Vlach, J. T3N46
Voo, T. T1A04
Vujovic, N.S. W3N39
Vukadinovic, M. T1D01
Vuori, J. T2N25
Wada, K. T1A02
Wada, M. W1N41
Wada, S. W4N49
Wahlroos, T. T1G02
Wakabayashi, S. M3C04
Walker, J. T2N01
Walley, J. T1G01
Wambacq, P. T2N48
Wambacq, P. W4C03
Wang, A. T2N15
Wang, C. W3C04
Wang, C.C. T4N42
Wang, C.C. W1N38
Wang, C.J. T1N40
Wang, C.K. W2N32
Wang, C.L. W3N08
Wang, C.L. W3N09
Wang, C.P. T3N22
Wang, C.S. M3N23
Wang, F. W3E03
Wang, H.O. T4F03
Wang, H.Y M4N21
Wang, J. W3N38
Wang, K. T1B03
Wang, K.C. W2N06
Wang, P.T. T4N44
Wang, T.S. W4N45
Wang, Z. M4N11
Wanhammar, R.L. T2D04
Waskiewicz, J. T2N34
Wassenaar, R.F. T3E03
Watanabe, T. M4N19
Watatani, Y. W1H01
Wawryn, K. T1N47
Wawryn, K. T1N43
Way, W.I. W2N32
Wei, C.H. T2N06
Wei, N. W2N38
Wei, Y. W3N38
Wendt, C. M4N08
Werner, F. W3N35
Wess, B. T3N10
Wey, C.L. T3N06
Wey, C.L. T3N22
Wey, C.L. M4N03
Wey, T. M3N22
Whitman, R.K. T4H04
Wiegerink, R.J. T3E03
Wilamowski, B. T2N38
Wilamowski, B.M. W1N27
Wilberg, J. T2N40
Wilkes, D.M. W3N21
Willis, J. T2N24
Willson, Jr., A.N. M4H02
Willson, Jr., A.N. W1D01
Willson, Jr., A.N.. W1G01
Wilson, C. T2F03
Wilson, D.M. T1N03
Wilson, W.C. T3N33
Wing, O. T2C01
Wintenberg, A. T2N01
Wise, K.D. W3G01
Wittenburg, J. W2N33
Wojciechowski, J. T3N45
Wolf, H.G. T4N43
Wong, D.F M3C03
Wong, D.F. M3C01
Wong, C. K. M3N15
Wong, C.K. M3C03
Wong, S.C. M4E04
Wosnitza, M. M4N13
Wrzyszcz, A. W3C02
Wu, A.K.M. M4G04
Wu, A.K.M. M4N45
Wu, A.Y. W1N32
Wu, C.W. T1D02
Wu, C.W. W4N36
Wu, C.Y. T3B03
Wu, C.Y. W1N33
Wu, C.Y. T2N02
Wu, D. W2N43
Wu, J.M. T4N42
Wu, K.Y. M4N45
Wu, X. T4H02
Wu, Y.P. W3E04
Wuertele, D. W1H01
Xia, X. M3N19
Xiao, C. W2N08
Xiao,C. W2N07
Xibilia, M.G. W4N42
Xing, Z. W1C03
Xiong, K. W4N50
Xu, G.F. M3N13
Xu, H. T4N12
Xu, N. T2N01
Xuan, B. W2D04
Yagi, H. W4N49
Yagyu, M. T4D02
Yahagi, T. W1N12
Yamada, A. W4N47
Yamakawa, T. W3B02
Yamasawa, A. W3G02
Yamashita, K. M3N11
Yamashita, Y. T3N35
Yamazaki, J. T2N29
Yamazaki, T. M4N14
Yang, F. T2A01
Yang, H.K. T3D04
Yang, H.T. T1E04
Yang, J.M. W1N43
Yang, R. T2N10
Yang, R. T1N10
Yang, S. W2N38
Yang, T. W. T2B03
Yang, W. T4N39
Yang, W. T2N37
Yang, W. M4F02
Yao, K. T2N15
Yardim, M. T2N07
Yau, S.F. W3H04
Yaz, E.E. W2N28
Yazdi, N. W3G01
Ye, H. T1B03
Yeh, M.H. W4N08
Yen, G. T4B03
Yim, Z.K. M3H01
Yin, S.C. W2N32
Yochelson, D. T2N34
Yoon, K.S. T2A04
Yoshida, N. M3C04
Yoshimoto, S. W2N18
Yost, S. M3N07
You, F. T3E02
Youan, K. T4N10
Young, G. T2N01
Yu, P.T. W1N37
Yu, Y. M4F01
Yuan, J. T1N29
Yue, Y. T4N10
Yuen, H. W1N14
Yufera, A. M3N02
Yuhas, B. M2B03
Yusim, I. M3N44
Zaghloul, M.E. W4B02
Zaghloul, M.E. M3N20
Zakhor, A. W4A03
Zeng, B. W3N16
Zeng, R. M4N06
Zeng, X. W3N04
Zerhouni, N. M4N20
Zerhouni, N. T1N15
Zhang, B. T4A03
Zhang, J.Y. T3N25
Zhang, P. W4N41
Zhang, Y. W1N26
Zhang, Y.Q. W2H05
Zhang, Z. W1N32
Zheng, J. W4N11
Zheng, W.X. M3N08
Zhong, W. T1E05
Zhu, G. M3N29
Zhu, J. T2H01
Zhu, K. M3C03
Zhu, L. W4A01
Zhu, L. T3N46
Zhu, W.P. W2N15
Zhu, Z. T3G02
Zoubi-AL, M. W2N20
Zurada, J.M. W1N05
Zurada, J.M. T2B04
Zurada, J.M. T3N40
Zurada, J.M. T3N41
Zurbach, P. W3H02
==========
Monday, 8:30 a.m. - 10:00 a.m. Keynote Session, Ballroom
M1
Chair: Phil Allen, General Chairman
8:30am to 8:45am - Introduction and welcome (Phil Allen and Don Bouldin)
8:45am to 9:30am - Dr. Jim Meindl, "A Prospectus for Low Power Gigascale
Integration (GSI)"
9:30am to 10am - Awards - Part I
James D. Meindl
Joseph M. Pettit Chair Professor of Microelectronics
Georgia Institute of Technology
Microelectronics Research Center
Atlanta, Georgia
BIOGRAPHICAL SKETCH
James D. Meindl is the Joseph M. Pettit Chair Professor of Microelectronics
at the Georgia Institute of Technology in Atlanta, Georgia. Previously he
served from 1986 to 1993 as Senior Vice President for Academic Affairs and
Provost of Rensselaer Polytechnic Institute in Troy, New York. From 1967
through 1986 he was with Stanford University where he was John M. Fluke
Professor of Electrical Engineering, Associate Dean for Research in the
School of Engineering, Director of the Center for Integrated Systems,
Director of the Electronics Laboratories, and founding Director of the
Integrated Circuits Laboratory. He is a co-founder of Telesensory Systems,
Inc., the principal manufacturer of electronic reading aids for the blind,
and served as a member of the Board from 1971 through 1984. From 1965
through 1967 he was Director of the Integrated Electronics Division at the
Fort Monmouth, New Jersey U.S. Army Electronics Laboratories. He received
his B.S., M.S. and PhD degrees in Electrical Engineering from
Carnegie-Mellon University in 1955, 1956 and 1958 respectively. He is the
author of a book on Micropower Circuits and over 300 technical papers on
ultra large scale integration, integrated electronics, and medical
electronics, and editor of a book, Brief Lessons in High Technology, which
elucidates the most important economic event of our lives, the emergence of
the information society. Dr. Meindl is a Fellow of the IEEE and the
American Association for the Advancement of Science and a member of the
American Academy of Arts and Sciences and the National Academy of
Engineering and its Academic Advisory Board. Dr. Meindl received the 1991
Benjamin Garver Lamme Medal from ASEE. He was the recipient of the 1990
IEEE Education Medal "for establishment of a pioneering academic program for
the fabrication and application of integrated circuits" and the recipient of
the 1989 IEEE Solid-state Circuits Medal for contributions to solid-state
circuits and solid-state circuit technology. At the 1988 IEEE International
Solid-state Circuits Conference, he received the Beatrice K. Winner Award.
In 1980 he was the recipient of the IEEE Electron Devices Society's J.J.
Ebers Award for his contributions to the field of medical electronics and
for his research and teaching in solid-state electronics. From 1970 through
1978 Dr. Meindl and his students received five outstanding paper awards at
IEEE International Solid-state Circuits Conferences, along with one received
at the 1985 IEEE VLSI Multilevel Interconnections Conference. His major
contributions have been a) new medical instruments enabled by custom
integrated electronics, b) projections and codification of the hierarchy of
physical limits on integrated electronics, and c) leadership in creation of
academic environments promoting high quality teaching and research.
Monday, 10:00 a.m. - 10:30 a.m. Break/Refreshments
Monday, 10:30 a.m. - 12:00 p.m., Room A
M2A00
Session Title: Overview of Analog Signal Processing
Chair: Angel Rodriguez-Vazquez
Centro Entro Nacional De Microelectronica,
Universidad De Sevilla, Sevilla, SPAIN
angel@cnm.us.es
M2A01
10:30 a.m. - 10:45 a.m.
General Overview of the Track
Angel Rodriguez-Vazquez
Centro Entro Nacional De Microelectronica,
Universidad De Sevilla, Sevilla, SPAIN
angel@cnm.us.es
10:45 a.m. - 11:05 a.m.
Analog Interfaces for Sensors
Franco Maloberti
University of Pavia, Pavia, ITALY
franco@ipvsp4.unipv.it
11:05 a.m. -- 11:30 a.m.
Design Strategies for Digital VLSI-Compatible A/D Interfaces
Carlos Leme and Jose Franca
Instituto Superior Tecnico, Lisbon, PORTUGAL
franca@ecsm4.ist.utl.pt
11:30 a.m. -- 11:55 a.m.
Passive Sigma-Delta Modulators for Mobile Communications
Bosco Leung
University of Waterloo, Waterloo, Canada
bleung@sun14.vlsi.uwaterloo.ca
Monday, 10:30 a.m. - 12:00 p.m., Room B
M2B00
Session Title: Overview of Neural Systems and Applications
Chair: Andreas G. Andreou
Johns Hopkins University, Baltimore, MD
andreou@jhunix.hcf.jhu.edu
M2B01
Andreas G. Andreou
Johns Hopkins University
andreou@jhunix.hcf.jhu.edu
M2B02
Kwabena Boahen
California Institute of Technology, Pasadena, CA
buster@pcmp.caltech.edu
M2B03
Paul Muller
Univ. of Pennsylvania
Monday, 10:30 a.m. - 12:00 p.m., Room C
M2C00
Session Title: Overview of Computer-Aided Design
Chair: D. F. Wong
University of Texas, Austin, TX
wong@cs.utexas.edu
M2C01
Network-Flow Based Circuit Partitioning
D.F. Wong
University of Texas, Austin, TX
wong@cs.utexas.edu
M2C02
Wavelet Method for High-Speed Circuit Simulation
Dian Zhou
University of North Carolina, Charlotte, NC
zhou@mosaic.uncc.edu
M2C03
Physical Design: R&D Needs and Directions for Deep Submicron
Andrew B. Kahng
University of California, Los Angeles, CA
abk@cs.ucla.edu
Monday, 10:30 a.m. - 12:00 p.m., Room D
M2D00
Session Title: Overview of Digital Signal Processing
Chair: I. Hartimo
Helsinki University of Technology, Helsinki, Finland
Iiro.Hartimo@hut.fi
M2D01
Overview of nonlinear stack and Boolean filtering for image processing
Moncef Gabbouj
Tampere University of Technology, Pori, Finland
gabbouj@pori.tut.fi
M2D02
Overview of multirate signal processing
Truong Nguyen
University of Wisconsin, Madison, WI
nguyen@ece.wisc.edu
M2D03
Overview of polynomial based image filtering
Giovanni Sicuranza (presented by M. Gabbouj)
Tampere University of Technology, Pori, Finland
gabbouj@pori.tut.fi
Monday, 10:30 a.m. - 11:15 a.m., Room E
M2E00
Session Title: Overview of Power Systems I
Chair: H. Mori
Meiji University, Kawasaki, JAPAN
hmori@isc.meiji.ac.jp
Speaker: H.D. Chiang, Cornell University, Ithaca, NY
Title: Direct Stability Assessment of Power Systems:
Recent Developments and New Challenges
Monday, 11:15 a.m. - 12:00 p.m., Room E
Session Title: Overview of Power Circuits
Chair: L. Martinez
Escola Tecnica Superior d'Enginyeria,URV, Tarragona, SPAIN
Speaker: TBA
Title: TBA
Monday, 10:30 a.m. - 12:00 p.m., Room F
M2F00
Session Title: Overview of Nonlinear Circuits & Systems
Chairs: Maciej Ogorzalek and Guanrong Chen
University of Mining and Metalurgy, Krakow, Poland
University of Houston, Houston, TX
maciej@fractal.zet.agh.edu.pl
gchen@uh.edu
M2F01
4101
Applied Aspects of Synthesized Chaotic Signals and Systems
Kevin Cuomo
mani@eecs.wsu.edu
M2F02
4102
Reconstruction of Nonlinear Systems
A. Mees
mani@eecs.wsu.edu
M2F03
4103
Intelligent Identification and Control of Chaotic Systems
G. Chen
University of Houston, Houston, TX
gchen@uh.edu
M2F04
4104
Control Strategies for Spatial-Temporal Systems and Neural Networks
M. Ogorzalek and M. Adachi
University of Mining and Metalurgy, Krakow, POLAND
Artificial Brain Systems Lab., Wako-shi, JAPAN
maciej@fractal.zet.agh.edu.pl
Monday, 10:30 a.m. - 12:00 p.m., Room G
M2G00
Session Title: Overview of VLSI Systems and Applications
Chairs: Magdy Bayoumi and Mona Zaghloul
University of Southwestern Louisiana, Lafayette, LA
George Washington University, Washington, DC
mab@cacs.usl.edu
zaghloul@seas.gwu.edu
M2G01
4001
MEMS and the IC Designer
Kristofer S. J. Pister
University of California, Los Angeles, CA
pister@icsl.ucla.edu
M2G02
4002
Simpler Approach to MEMS Design and Its Application to Medical and
Health Care Technologies
Ash Parameswaran
Simon Fraser University, Burnaby, CANADA
param@cs.sfu.ca
M2G03
4003
Surface-MicroMachined Sensing Systems New Paradigm for the 21st Century
Richard S. Payne
Analog Devices, Wilmington, MA
Richie.Payne@analog.com
M2G04
4004
Methodology for Integrated MEMS Design
Steven L. Garverick and Mehran Mehregany
Case Western Reserve University, Cleveland, OH
slg9@po.cwru.edu
mehran@mems4.eciv.cwru.edu
M2G05
4005
Microheating Elements in CMOS Technology
Michael Gaitan
NIST, Gaithersburg, MD
gaitan@eeel.nist.gov
Monday, 10:30 a.m. - 12:00 p.m., Room H
M2H00
Session Title: Overview of Visual Signal Processing
Chair: P. Pirsch
University of Hannover, GERMANY
pirsch@tnt.uni-hannover.de
M2H01
4301
Recent Advances in Video Compression
Bernd Girod
University of Erlangen-Nuernberg, Erlangen, GERMANY
girod@nt.e-technik.uni-erlangen.de
M2H02
4302
Digital Transmission Technologies for Video Communications: An Overview
Russell T. Hsing
Bellcore, Morristown, NJ
trh@thumper.bellcore.com
Monday, 12:00 p.m. -- 1:30 p.m., Lunch Break
Monday, 1:30 p.m. -- 3:00 p.m., Room A
M3A00
Session Title: Analog Signal Processing -- Delta-Sigma Techniques I
Chair: G. W. Roberts
McGill University, Montreal, CANADA
roberts@macs.ee.mcgill.ca
M3A01
A1101
1294_benoitv
FM Signal Generation Using Delta-Sigma Oscillators
B.R. Veillette and G.W. Roberts
McGill University, Montreal, QC, CANADA
benoitv@macs.ee.mcgill.ca
M3A02
A1102
0380_srn
A Minimal Multibit Digital Noise Shaping Architecture
S. R. Norsworthy, D. A. Rich and T. R. Viswanathan
AT&T Bell Laboratories, Allentown, PA and Texas Instruments
74763.647@compuserve.com
M3A03
A1103
0271_thk
An Efficient Design Method for the Modulator of High-Order Sigma-Delta ADCs
J. Chen and T. Kuo
National Cheng Kung University Taiwan, TAIWAN, ROC
thk@sparc20.ee.ncku.edu.tw
M3A04
A1104
0720_morche
A New Multistage Bandpass Sigma-Delta Modulator
A. Aubert, D. Morche, E. Andre, F. Balestro and P. Senn
France Telecom, CNET-CNS Grenoble, Meylan, FRANCE
morche@cns.cnet.fr
Monday, 1:30 p.m. -- 3:00 p.m., Room B
M3B00
Session Title: Neural Systems and Applications -- Neuromorphic Analog VLSI I
Chair: Tor Sverre Lande
University of Oslo, Oslo, NORWAY
bassen@ifi.uio.no
M3B01
A7101
3701_andreas
Retinomorphic Systems I: Pixel Design
Kwabena Boahen
California Institute of Technology, Pasadena, CA
buster@pcmp.caltech.edu
M3B02
A7102
1496_rahul2
An Analog VLSI Cochlea with New Transconductance Amplifiers
and Nonlinear Gain Control
R. Sarpeshkar, R. Lyon and C. Mead
Caltech and Apple Computer, CA
rahul@pcmp.caltech.edu
M3B03
A7103
0035_djma
A Pulsed VLSI RADIAL Basis Function Chip
D.J. Mayes, A. Hamilton, A.F. Murray, H.M. Reekie
University of Edinburgh, Edinburgh, SCOTLAND, UK
djma@ee.ed.ac.uk
M3B04
A7104
1009_adreas
A circuit model of hair-cell transduction for asynchronous
analog auditory feature extraction
N. Kumar, G. Cauwenberghs and A.G. Andreou
Johns Hopkins University, Baltimore, MD
andreou@jhunix.hcf.jhu.edu
Monday, 1:30 p.m. -- 3:00 p.m., Room C
M3C00
Session Title: Computer-Aided Design -- Performance-Driven Routing
Chair: Chung-Kuan Cheng
University of California, San Diego, CA
kuan@cs.ucsd.edu
M3C01
A8101
1028_ccp
Fast Algorithms for Optimal Wire-Sizing Under Elmore Delay Model
C.-P. Chen and M. D.F. Wong
Universiy of Texas at Austin, Austin, TX
ccp@cs.utexas.edu
M3C02
A8102
0292_joh
Constructing Minimal Spanning/Steiner Trees with Bounded Path Length
J. Oh, I. Pyo and M. Pedram
University of Southern California, Los Angeles, CA
joh@usc.edu
M3C03
A8103
1385_yaowen
On a New Timing-Driven Routing Tree Problem
Y.-W. Chang, D. F. Wong, K. Zhu and C.K. Wong
University of Texas at Austin, Austin, TX
AT&T Bell Laboratories, Naperville, IL
Chinese University of Hong Kong, HONG KONG
yaowen@cs.utexas.edu
M3C04
A8104
0193_koide
A Timing-Driven Global Routing Algorithm Considering
Channel Density Minimization for Standard Cell Layout
T. Suzuki, T. Koide, S. Wakabayashi and N. Yoshida
Hiroshima University, Higashi-Hiroshima, JAPAN
koide@ecs.hiroshima-u.ac.jp
wakaba@ecs.hiroshima-u.ac.jp
Monday, 1:30 p.m. -- 3:00 p.m., Room D
M3D00
Session Title: Digital Signal Processing -- Nonlinear DSP I
Chair: I. Pitas
Aristotle University of Thessaloniki, Thessaloniki, GREECE
pitas@zeus.csd.auth.gr
M3D01
A2101
0378_pitas
Sorting Networks Using Nonlinear Lp Mean Comparators
M. Pappas and I. Pitas
Aristotle University of Thessaloniki, Thessaloniki, GREECE
pitas@zeus.csd.auth.gr
M3D02
A2102
0037_douglas
An Efficient Algorithm for Running Max/Min Calculation
S.C. Douglas
University of Utah, Salt Lake City, UTAH
douglas@ee.utah.edu
M3D03
A2103
0757_taguchi
Adaptive Weighted Median Filters by Using Fuzzy Techniques
M. Meguro and A. Taguchi
Musashi Institute of Technology, Tokyo, JAPAN
uatuguci@ipc.musashi-tech.ac.jp
M3D04
A2104
1063_huang
Updator-Shared Adaptive Parallel Equalization (U-SHAPE)
Using Set-Membership Identification
S. Gollamudi and Y.F. Huang
University of Notre Dame, IN
huang.2@nd.edu
Monday, 1:30 p.m. -- 3:00 p.m., Room E
M3E00
Session Title: Power Circuits and Systems -- Power Electronics Topologies
Chair: H. Chung
City University of Hong Kong, Hong Kong
eeshc@cityu.edu.hk
M3E01
A5101
0815_rgiral
Self-Oscillating Boost Converter with Output Filter for
Ideal Load Regulation
R.Giral, J.Font, L.Martinez, J.Calvente, R.Ceyua and E.Fossas
Escola Tecnica Superior d'Enginyeria,URV, Tarragona, SPAIN
Escola University dÕEnginyeria Tecnica, UPC, Manresa, SPAIN
Dept. Matematica Aplicada, UPC, Barcelona, SPAIN
rgiral@etse.urv.es
M3E02
A5101
0258_lambert
A Family of PWM Soft-Switching Converters with Low Stresses
of Voltage and Current
M.S. Vilela, E.A.A. Coelho, J.B. Vieira Jr., L.C. de Freitas and V.J. Farias
Universidade Federal de Uberlandia, Uberlandia, BRAZIL
FREITAS@BRUFU.BITNET
M3E03
A5101
0664_renlin
ZCS and ZVS Power Factor Correction
B.-R. Lin and t.-S. Huang
National Yunlin Institute of Technology, Yunlin, TAIWAN, ROC
M3E04
A5101
0045_eeshc2
Switched-Capacitor-Based DC-to-DC Converter With Improved
Input Current Waveform
H. Chung, and A. Ioinovici
City University of Hong Kong, Kowloon Tong, HONG KONG
Holon Institute for Technological Education, ISRAEL
eeshc@cityu.edu.hk
Monday, 1:30 p.m. -- 3:00 p.m., Room F
M3F00
Session Title: Nonlinear Circuits & Systems -- Nonlinear Circuits
Chair: Michael Green
State University of New York at Stony Brook, NY
mgreen@ee.sunysb.edu
M3F01
A4101
0608_davis
Analysis of Delay Circuits and Systems Using Operators and Causality
A. Davis
San Jose State University, San Jose, CA
adavis@isc.sjsu.edu
M3F02
A4102
1258_mgreen
New Topological Criteral for Modeling Reactive Elements in
Nonlinear Circuits
M. Green
State University of New York at Stony Brook, NY
mgreen@ee.sunysb.edu
M3F03
A4103
1113_nishi
A Transistor Circuit Can Possess Infinitely Many Solutions
Under the Assumption that the First and the Second Derivatives
of the V-I Curves of Nonlinear Resistors are Positive
T. Nishi
Kyushu University, Fukuoka, JAPAN
nishi@csce.kyushu-u.ac.jp
M3F04
A4104
0218_petarv
A Method for Automatic Generation of Piecewise Linear Models
P. Veselinovic and D. Leenaerts
Eindhoven University of Technology, Eindhoven, NETHERLANDS
petarv@eeb.ele.tue.nl
Monday, 1:30 p.m. -- 3:00 p.m., Room G
M3G00
Session Title: VLSI Systems and Applications -- Power Reduction and Estimation
Chair: Steve Kang
University of Illinois at Urbana-Champaign, Urbana, IL
kang@uivlsi.csl.uiuc.edu
M3G01
A6101
0222_shanbhag
A Fundamental Basis for Power-Reduction in VLSI Circuits
N.R. Shanbhag
University of Illinois at Urbana-Champaign, Urbana, IL
shanbhag@uivlsi.csl.uiuc.edu
M3G02
A6102
0063_hillam2
Simulation-Based Maximum Power Estimation
A. Hill, C. Teng and S. Kang
University of Illinois at Urbana-Champaign, Urbana, IL
hillam@uivlsi.csl.uiuc.edu
M3G03
A6103
1062_hnguyen
Activity Measures for Fast Relative Power Estimation
Directed Numerical Transformations for Low Power DSP Synthesis
H.T. Nguyen and A. Chatterjee
Georgia Institute of Technology, Atlanta, GA
hnguyen@ee.gatech.edu
M3G04
A6104
1333_salsano_cardarilli
Bus Architecture for Low Power VLSI Digital Circuits
G.C. Cardarilli, M.Salmeri, A.Salsano and O.Simonelli
Tor Vergata University, Roma, ITALY
salsano@utovrm.it
Monday, 1:30 p.m. -- 3:00 p.m., Room H
M3H00
Session Title: Visual Signal Processing -- Video Coding I
Chair: Alan Willson
University of California, Los Angeles, CA
willson@ee.ucla.edu
M3H01
A3101
0609_zungkon
Temporally Adaptive Motion Estimation Using Temporal Subband Analysis
Z.K. Yim and J.J. Chung
Inha University, Incheon, KOREA
zungkon@dragon.inha.ac.kr
M3H02
A3102
0307_damon
Regularized Estimation of Occluded and Discontinuous Displacement
Vector Fields Using Robust Entropic Functionals
D. L. Tull and A. K. Katsaggelos
Northwestern University, Evanston, IL
damon@eecs.nwu.edu
M3H03
A3103
0669_nogu
MPEG Video Compositing in the Compressed Domain
Y. Noguchi, D.G. Messerschmitt and S.-F. Chang
Asahi Chemical Industry Co., Ltd., Kanagawa, JAPAN
University of California, Berkeley, CA
Columbia University, New York, NY
nogu@ljk.atsugi.asahi-kasei.co.jp
M3H04
A3104
1190_jmeng
Buffer Control Techiniques for Compressed-Domain Video Editing
J. Meng and S.F. Chang
Columbia University & Center for Telecommunications Research, New York, NY
jmeng@ctr.columbia.edu
Monday, 1:30 p.m. -- 3:00 p.m., Room N, Poster Sessions
M3N00
Session Title: Analog Signal Processing -- A/D and D/A Converters
Chair: Adoracion Rueda
M3N01
A1111
0427_nowr
A General Approach to the AC and DC Analysis of a Class of
Sigma-Delta Modulator Configurations
T.P. Borsodi and B. Nowrouzian
University of Calgary, Calgary, AB, CANADA
nowr@enel.ucalgary.ca
M3N02
A1112
1384_yufera
A Switched-Current Incremental A/D Converter
A. Yufera and A. Rueda
Centro Nacional de Microelectronica, Univ. de Sevilla, Sevilla, Spain
yufera@cnm.us.es
M3N03
A1113
1047_fischer
A Sigma-Delta Modulator Architecture for Wide Bandwidth Applications
G. Fischer and A. Davis
University of Rhode Island, Kingston, RI
fischer@ele.uri.edu
M3N04
A1114
0785_kuo
Sigma-Delta Modulator for Bandpass Signal
C.J. Kuo, C.T. Liu and C.J. Hou
National Chung Cheng University, Chiayi, TAIWAN, ROC
kuo@ee.ccu.edu.tw
M3N05
A1115
0527_nairn
Trimming of Current Mode DACs by Adjusting Vt
A. Biman and D.G. Nairn
Queen's University, Kingston, ON, CANADA
nairn@eleceng.queensu.ca
M3N06
A1116
1027_carlos
Architectures for A/D Conversion with Optimal Use of Oversampling
D. Rocha, C. Azeredo Leme and J. Franca
Superior Tech. Institute, Lisboa, Codex, PORTUGAL
carlos@ecsm4.ist.utl.pt
M3N06a
Session Title: Digital Signal Processing -- Adaptive Filtering I
Chair: M. Najim
Equipe Signal et Image, Enserb, FRANCE
najim@goelette.tsi.u-bordeaux.fr
M3N07
A2111
0127_syost
Stability of Shift-Variant Difference Equations with Application
to Adaptive Digital Filters
S. Yost and P. Bauer
University of Notre Dame, Notre Dame, IN
pbauer@mars.ee.nd.edu
M3N08
A2112
0132_zheng2
Fast Convergence Algorithms for the Adaptive Envelope-Constrained
Filter Design
W. X. Zheng
University of Western Sydney, Nepean, Sydney, AUSTRALIA
zheng@st.nepean.uws.edu.au
M3N09
A2113
0221_khasawneh3
Analysis of an LMS-Based Algorithm Using Reduced Number of Computations
J.M. Abu-Ghalune and M.A. Khasawneh
Jordan University of Science & Technology, Irbid, JORDAN
mkha@amra.nic.gov.jo
M3N10
A2114
0621_muneyasu
Parallel-Form Realization of 2-D Adaptive Separable-Denominator
State-Space Filters
M. Muneyasu and T. Hinamoto
Hiroshima University, Higashi-Hiroshima, JAPAN
muneyasu@ecl.sys.hiroshima-u.ac.jp
M3N11
A2115
0660_naka
A Two-Dimensional Adaptive Joint-Process Estimator using New Lattice Form
T. Nakachi, K. Yamashita and N. Hamada
Keio University, Yokohama-shi, JAPAN
University of the Ryukyus, Nishihara, Okinawa-ken, JAPAN
naka@tkhm.elec.keio.ac.jp
M3N12
A2116
1019_belt
Laguerre Filters with Adaptive Pole Optimization
H.J.W. Belt and A.C. den Brinker
Eindhoven University of Technology, Eindhoven, NETHERLANDS
H.J.W.Belt@ele.tue.nl
M3N12a
Session Title: Visual Signal Processing -- Image Restoration and Segmentation
Chair: A. K. Katsaggelos
Northwestern University, Evanston, IL
aggk@eecs.nwu.edu
W4N48 -- TO BE PRESENTED IN PLACE OF M3N13
A8916
1469_hoisko
Specification, Hardware Implementation and Prototyping Environment
for Image Processing Algorithms
S. Hoisko, H. Hakkarainen, K. Vihavainen and J. Isoaho
Tampere University of Technology, Tampere, FINLAND
hoisko@cs.tut.fi
M3N13 -- WITHDRAWN
A3111
1363_tbose
Image Restoration Using a Conjugate Gradient Based Adaptive Algorithm
K.S. Joo, T. Bose and G.F. Xu
University of Colorado, Denver, CO
tbose@carbon.cudenver.edu
M3N14
A3112
1371_stevensochoy
Optimal Choice of Local Regularization Weights in Iterative
Image Restoration
S. S. O. Choy, Y. H. Chan, and W. C. Siu
Hong Kong Polytechnic University, HONG KONG
enyhchan@hkpucc.polyu.edu.hk
M3N15
A3113
1509_eeau
Motion Compensated Temporal Interpolation with Overlapped Transform
Chi-Kong Wong and Oscar C. Au
Hong Kong Univ. of Science and Technology, Hong Kong
eeau@ee.ust.hk
M3N16
A3114
0626_hksong
Edge-Based Segmentation Algorithm for Range Image using
Pseudo-Reflectance Image
H.K. Song and J.S. Choi
Chung Ang University, Seoul, KOREA
songhk@hdtv2.ee.cau.ac.kr
M3N17
A3115
0617_huang2
Contour Refinement by Enhanced Query-Based Learning
S.-J. Huang and C.-C. Hung
Kaohsiung Polytechnic Institute, TAIWAN, ROC
University of Texas, Austin, TX
clhuang@mail.ncku.edu.tw
M3N18
A3116
0342_kramer
Analog VLSI Motion Discontinuity Detectors for Image Segmentation
J. Kramer, R. Sarpeshkar and C. Koch
California Institute of Technology, Pasadena, CA
kramer@klab.caltech.edu
M3N19
1560
A Thresholding Hierarchial Block Matching Algorithm for Motion Estimation
X. Xia and Y.Q. Shi
New Jersey Institute of Tech. Newark N.J. USA
shi@tesla.njit.edu
M3N19a
Chaos and Bifurcations
Chair:
M3N20
A4111
1154_veljko
Sychronization of Chaotic Neural Networks for Secure Communications
V. Milanovic and M. E. Zaghloul
The George Washington University, Washington, DC
veljko@seas.gwu.edu
M3N21
A4112
1396_alex
Controlling Chaotic Oscillations Using Feedback and Directional Coupling
A.K. Kozlov and V.D. Shalfeev
University of Nizhny Novgorod, RUSSIA
alex@hale.appl.sci-nnov.ru
M3N22
A4113
0654_twey
A Negative Feedback Chaotic Circuit Design
T. Wey and L. Ogborn
Purdue University, West Lafayette, IN
wey@ecn.purdue.edu
M3N23
A4114
1185_chiang
The Fast Computation for Saddle-Node Bifurcation Points of
General Nonlinear System with Decoupled Parameters
H.-D. Chiang, C.-S. Wang and R. Jean-Jumeau
Cornell University, Ithaca, NY
chiang@ee.cornell.edu
M3N24
A4115
0837_moros
Bifurcation Phenomena in Wien-Bridge Oscillators Coupled by One Resistor
S. Moro and S. Mori
Keio University, Yokohama, JAPAN
moro@mori.elec.keio.ac.jp
M3N25
A4116
0957_kohshi
On the Bifurcations of Subharmonic Oscillations in Nonlinear
Three-Phase Circuit
K. Okumura and T. Hisakado
Kyoto University, Kyoto, JAPAN
kohshi@kuee.kyoto-u.ac.jp
M3N25a
Session Title: Power Circuits and Systems -- Power Electronics Topologies
Chair: L. C. de Freitas
Universidade Federal de Uberlandia, Uberlandia, BRAZIL
FREITAS@BRUFU.BITNET
M3N26
A5101
0265_pereira
A New ZC-ZVS Forward Converter
A.A. Pereira, E.A.A. Coelho, V.J. Farias, L.C. de Freitas and J.B. Vieira Jr.
Universidade Federal de Uberlandia, Uberlandia, BRAZIL
BATISTA@BRUFU.BITNET
paulo@ele.puc-rio.br
M3N27
A5101
0262_tofano
A Self-Resonant-PWM Boost Converter with Unity Power Factor
Operation by Using a Bang-Bang Current Control Strategy with
Fixed Switching Frequency
R. Tofano Jr., C.H. Treviso, V.J. Farias, J.B. Vieira Jr. and L.C. de Freitas
Universidade Federal de Uberlandia, Uberlandia, BRAZIL
FREITAS@BRUFU.BITNET
M3N28
A5101
1315_shamala
A new high-voltage variable-frequency resonant-commutated converter
S. A. Chickamenahalli and J. J. Cathey
Wayne State University, Detroit, MI
University of Kentucky, Lexington, KY
shamala_chickamenahalli@hub.eng.wayne.edu
M3N29
A5101
1337_eeadloin_hkpucc
Switched-Capacitor Power Supplies: DC Voltage Ratio, Efficiency,
Ripple, Regulation
G. Zhu and A. Ioinovici
Hong Kong Polytechnic University, HONG KONG
Institute for Technology, Holon, ISRAEL
adrian@milk.cteh.ac.il
M3N30
A5101
0260_oliveira
Soft Switching Power Amplifiers for Audio Applications
R.C. Oliveira, E.A.A. Coelho, J.B. Vieira Jr., L.C. de Freitas and V.J. Farias Universidade Federal de Uberlandia, Uberlandia, BRAZIL
FREITAS@BRUFU.BITNET
M3N31
A5101
0735_cirstea
A Complete ASIC Controlled Electric Drive System
M.N. Cirstea, E.B. Patterson, D. Morley and P.G. Holmes
Nottingham Trent University, Nottingham, UK
ca153mnc01@ntu.ac.uk
M3N31a
Evolable Hardware and Circuit Reconfiguration
Chair: A. Stauffer
EPFL, Lausanne, SWITZERLAND
Andre.Stauffer@di.epfl.ch
M3N32
A6111
3101
The incremental reconfiguration capabilities of the CAL FPGA family
John Gray
Xilinx Corp, Edinburgh, SCOTLAND
jpg@xilinx.com
M3N33
A6112
3102
Embryonics: development of a new family of coarse-grained FPGA
Daniel Mange
Swiss Federal Inst. of Technology, Lausanne, SWITZERLAND
mange@di.epfl.ch
M3N34
A6113
3103
Evolvable hardware with genetic learning
Tetsuya Higuchi
Electrotechnical Lab, Ibaraki, JAPAN
higuchi@etl.go.jp
M3N35
A6114
3104
Evolvable hardware with development
Hiroaki Kitano
Sony Corp., Tokyo, JAPAN
kitano@csl.sony.co.jp
M3N36
A6115
3105
Unconstrained evolution and hard consequences
Inman Harvey and Adrian Thompson
University of Sussess, Brighton, ENGLAND
inmanh@cogs.susx.ac.uk
adrianth@cogs.susx.ac.uk
M3N37
A6116
0191_hkutuk
A Field Programmable Analog Array Using Switched Capacitor Techniques
H. Kutuk and S.M. Kang
University of Illinois at Urbana-Champaign, IL
hkutuk@uivlsi.csl.uiuc.edu
M3N37a
Session Title: Neural Systems and Applications -- Theory and Applications
Chair: Stanislaw Jankowski
Warsaw University of Technology, Warsaw, POLAND
M3N38
A7111
0278_asarajed
Conditional Density Estimation with a Neural Network Using the GEM Algorithm
A. Sarajedini and P.M. Chau
University of California, San Diego, La Jolla, CA
asarajed@ece.ucsd.edu
M3N39
A7112
1458_sunfang
A New Speech Recognition System Using SOM and MLP Neural Networks
S. Fang and H. Guangrui
Shanghai Jiao Tong University, Shanghai, CHINA
M3N40
A7113
0652_andreas2
Classification of Lidar Waveforms by Neural Networks
D. Bhattacharya, R. Pillai and A. Antoniou
University of Victoria, BC, CANADA
andreas@ece.uvic.ca
M3N41
A7114
1269_gabi
Hand Written Digits Recognition Using Hough Transform and Neural Networks
G. Castellano and M. B. Sandler
King's College London, London, UK
m.sandler@kcl.ac.uk
gabi@orion.eee.kcl.ac.uk
M3N42
A7115
1373_creech
Artificial Neural Networks for Accurate High Frequency CAD Applications
G.L. Creech, B. Paul, C. Lesniak, T. Jenkins, R. Lee and K. Brown
Wright Laboratory, Wright-Patterson AFB, OH
creech@el.wpafb.af.mil
M3N43
A7116
0588_kawaguti
3-D Object Recognition Using a Genetic Algorithm
T. Kawaguchi and T. Baba
Oita University, Oita, JAPAN
kawaguti@csis.oita-u.ac.jp
M3N43a
Computer-Aided Design
Chair:
M3N44
A8111
0188_ilya
Analysis of Switched-Capacitor and Switched-Current Networks
with Complete Settling Assumption
I. Yusim and K. Suyama
Columbia University, New York, NY
ilya@elab.columbia.edu
M3N45
A8112
0198_yikan
Improvements on Chip-Level Electrothermal Simulator - ILLIADS-T
Y.K. Cheng, E. Rosenbaum and S.M. Kang
University of Illinois at Urbana-Champaign, Urbana, IL
yikan@uivlsi.csl.uiuc.edu
M3N46
A8113
0352_chris
Simple Solutions for Modeling The Non-Uniform Substrate Doping
C. Lallement, C.C. Enz and M. Bucher
Swiss Federal Institute of Technology, Lausanne, SWITZERLAND
christophe.lallement@leg.de.epfl.ch
M3N47
A8114
0848_bouchakour
Modeling and Characterization of the nMOS Transistor
Stressed by Hot-Carrier Injection
R. Bouchakour, L. Hardy, I. Limbourg, M. Jourdain and M. Jelloul
Telecom-Paris, Paris, FRANCE
University de Reims, Reims, FRANCE
bouchakour@amon.enst.fr
M3N48
A8115
1051_fychang
Travelling-wave Simulation of Diode Charge Storage Effect
F.-Y. Chang and K.P. Pun
The Chinese University, Shatin, New Territories, HONG KONG
fychang@ee.cuhk.hk
M3N49
A8116
1474_sheu
An Improved Method for MOS Transistor Output Conductance
S.H. Jen, Y. Oshima and B.J. Sheu
University of Southern California, Los Angeles, CA
sheu@pacific.usc.edu
Monday, 3:30 p.m. -- 5:00 p.m., Room A
M4A00
Session Title: Analog Signal Processing -- Analog Design Techniques
Chair: Frode Larsen
AT&T Bell Laboratories, Allentown, PA
larsen@aloft.att.com
M4A01
A1201
0724_larsen4
A low distortion driver for 3V operation
F. Larsen
AT&T Bell Laboratories, Allentown, PA
larsen@aloft.att.com
M4A02
A1202
0751_nikolay2
VCO with Double Cross-Coupled High-Speed and Low-Power
Multivibrator Architecture
N. Tchamov, A. Popov and P. Jarske
Tampere University of Technology, Tampere, FINLAND
nikolay@cs.tut.fi
M4A03
A1203
0583_moen
An Exponential-Law Element with Temperature Compensation
S.D. Moen and B. Dahl
SINTEF, Oslo, NORWAY
IC Consult, Skollenborg, NORWAY
Sverre.Dale.Moen@si.sintef.no
M4A04
A1204
0535_ajpayne
Linear Transfer Function Synthesis Using Non-Linear IC Components
A. Payne and C. Toumazou
Imperial College of Science and Technology, London, UK
a.j.payne@ic.ac.uk
Monday, 3:30 p.m. -- 5:00 p.m., Room B
M4B00
Session Title: Neural Systems and Applications -- Neuromorphic Analog VLSI II
Chair: Steve DeWeerth
Georgia Institute of Technology, Atlanta, GA
steve.deweerth@ece.gatech.edu
M4B01
A7201
1212_paul
An Autozeroing Amplifier Using pFET Hot-Electron Injection
P. Hasler, B.A. Minch, C. Diorio and C. Mead
California Institute of Technology Pasadena, CA
paul@hobiecat.pcmp.caltech.edu
M4B02
A7202
1120_rahul
Nonvolatile Correction of Q-offsets and Instabilities in Cochlear Filters
R. Sarpeshkar, R. F. Lyon and C. A. Mead
California Institute of Technology, Pasadena, CA
Apple Computer, Cupertino, CA
rahul@pcmp.caltech.edu
M4B03
A7203
1052_gert
Analog VLSI Long-Term Dynamic Storage
G. Cauwenberghs
Johns Hopkins University, Baltimore, MD
gert@jhunix.hcf.jhu.edu
M4B04
A7204
1056_harris
Analog VLSI Implementations of Continuous-Time Memory Structures
J. Juan, J.G. Harris and J.C. Principe
University of Florida, Gainesville, FL
harris@knicks.ee.ufl.edu
Monday, 3:30 p.m. -- 5:00 p.m., Room C
M4C00
Session Title: Computer-Aided Design -- Timing Optimization
Chair: D. F. Wong
University of Texas, Austin, TX
wong@cs.utexas.edu
M4C01
A8201
0287_jlillis
Algorithms for Optimal Introduction of Redundant Logic
for Timing and Area Optimization
J. Lillis, C.K. Cheng and T.T.Y. Lin
University of California at San Diego, La Jolla, CA
kuan@cs.ucsd.edu
M4C02
A8202
1215_papachristou_2
False Path Exclusion in Delay Analysis of RTL-Based
Datapath--Controller Designs
M. Nourani and C. Papachristou
Case Western Reserve University, Cleveland, OH
cap@alpha.cwru.edu
M4C03
A8203
0521_du1
A New Gate Selection Method for Resizing to Circuit
Performance Optimization
J. Kim, Y. Hsu and D.H.C. Du
University of Minnesota, Minneapolis, MN
du@cs.umn.edu
jhkim@cadence.com
M4C04
A8204
1141_tglee
Timing Optimization Algorithm for Design of High Performance
and Reliable VLSI Systems
T. Lee and H. Chang
Soongsil University, Seoul, KOREA
tglee@venus.soongsil.ac.kr
Monday, 3:30 p.m. -- 5:00 p.m., Room D
M4D00
Session Title: Panel on the Future of Digital Signal Processing
Chair: Sanjit K. Mitra
University of California, Santa Barbara, CA
mitra@ece.ucsb.edu
M4D01
4201
Future Challenges in DSP -- An Overview
Sanjit K. Mitra
University of California, Santa Barbara, CA
mitra@ece.ucsb.edu
M4D02
4202
Future Trends in DSP Chips
Takao Nishitani
NEC Corp., Kawasaki, JAPAN
takao@tsl.cl.nec.co.jp
M4D03
4203
Future Challenges in Telecommunication Applications of DSP
Maurice Bellanger
CNAM, Paris, FRANCE
bellang@cnam.cnam.fr
M4D04
4204
Future Challenges in Consumer Electronics Applications of DSP
Panos Papamichalis
Texas Instruments, Dallas, TX
panos@hc.ti.com
M4D05
4205
Future Challenges in DSP Algorithms and Architecture Designs for VLSI
Keshab Parhi
University of Minnesota, Minneapolis, MN
parhi@ee.umn.edu
M4D06
4206
Future Challenges in Mixed Analog-Digital Signal Processing
J. E. Franca
Instituto Superior Tecnico, Lisbon, PORTUGAL
franca@ecsm4.ist.utl.pt
Monday, 3:30 p.m. -- 5:00 p.m., Room E
M4E00
Session Title: Power Circuits and Systems -- Simulation of Power
Electronic Circuits
Chair: A. Ioinovici
Holon Institute for Technological Education, Holon, ISRAEL
adrian@milk.cteh.ac.il
M4E01
A5101
0008_amassari
A New Representation of DIRAC Impulses in Time-Domain
Computer Analysis of Networks with Ideal Switches
A. Massarini and M. K. Kazimierczuk
Universita' di Modena, Modena, ITALY
amassari@valhalla.cs.wright.edu
M4E02
A5101
1290_desanto4
An Optimized Method for the Time Domain Analysis of Switched RLC Networks
N. Femia and V. Tucci
University di Salerno, Fisciano, ITALY
femia@diiie.unisa.it
M4E03
A5101
0816_fcalven
Subharmonics, Bifurcations and Chaos in a Sliding-Mode
Controlled Boost Switching Regulator
J. Calvente, F. Guinjoan, L. Martinez and A. Poveda
Escola Tecnica Superior d'Enginyeria,URV, Tarragona, SPAIN
Escola Tecnica Sup. d'Engin. de Telecom., UPC, Barcelona, SPAIN
Polytechnical University of Catalonia, SPAIN
fcalven@etse.urv.es
M4E04
A5101
0594_swng
AC Analysis of SMPS
S.W. Ng, S.C. Wong and Y.S. Lee
Hong Kong Polytechnic University, Kowloon, HONG KONG
swng@encserver.en.polyu.edu.hk
Monday, 3:30 p.m. -- 5:00 p.m., Room F
M4F00
Session Title: Nonlinear Circuits & Systems -- Nonlinear Dynamics
Chair: Artice Davis
San Jose State University, San Jose, CA
adavis@isc.sjsu.edu
M4F01
A4201
0418_yuyi
Near-Optimal Construction of Wavelet Networks for
Nonlinear System Modeling
Y. Yu, S. Tan, J. Vandewalle and E. Deprettere
National University of Singapore, SINGAPORE
Leuven Catholic University, Heverlee, BELGIUM
Delft University of Technology, Delft, NETHERLANDS
eletansh@leonis.nus.sg
M4F02
A4202
1305_steiner_wang
Stability of High Order Sigma-Delta Modulators
P. Steiner and W. Yang
Harvard University, Cambridge, MA
woody@eecs.harvard.edu
M4F03
A4203
0936_parena
Dynamics of State Controlled CNNs
P. Arena, S. Baglio, L. Fortuna and G. Manganaro
University of Catania, Catania, ITALY
parena@dees.unict.it
M4F04
A4204
0787_saberi
Stability Analysis of Continuous Time Planar Systems
with State Saturation Nonlinearity
R. Mantri, A. Saberi and V. Venkatasubramanian
Washington State University, Pullman, WA
saberi@eecs.wsu.edu
Monday, 3:30 p.m. -- 5:00 p.m., Room G
M4G00
Session Title: VLSI Systems and Applications -- Low Power Adders/Multipliers
Chair: Magdy Bayoumi
University of Southwestern Louisiana, Lafayette, LA
mab@cacs.usl.edu
M4G01
A6201
0294_tormod
Power Consumption and Performance of Low-Voltage Bit-Serial Adders
T.Njoelstad and E.J.Aas
Norwegian Institute of Technology, Trondheim, NORWAY
tormod@fysel.unit.no
M4G02
A6202
1489_mab
A New Cell for Low Power Adders
E. Abu-Shama, A. Elchouemi. S. Sayed and M. Bayoumi
University of Southwestern Louisiana, Lafayette, LA
mab@cacs.usl.edu
M4G03
A6203
0043_eby
A Hybrid Radix-4/Radix-8 Low Power, High Speed Multiplier
Architecture for Wide Bit Widths
B. S. Cherkauer and E. G. Friedman
Intel Corporation, Santa Clara, CA
University of Rochester, Rochester, NY
friedman@ee.rochester.edu
M4G04
A6204
1074_eeawueed
High Performance Adder Cell for Low Power Pipelined Multiplier
A. Wu
City University of Hong Kong, HONG KONG
eeawueed@cityu.edu.hk
Monday, 3:30 p.m. -- 5:00 p.m., Room H
M4H00
Session Title: Visual Signal Processing -- Video Coding II
Chair: Sarah Rajala
North Carolina State University, Raleigh, NC
sar@eos.ncsu.edu
M4H01
A3201
0111_przemek2
Morphological Segmentation Based Video Coding Employing
Conditional Smoothing
P.J. Czerepinski and D.R. Bull
University of Bristol, Bristol, UK
Dave.Bull@Bristol.ac.uk
M4H02
A3202
0143_willson1
Design of a Memory-Efficient IIR Filter Bank with Application
to Subband Coding of Image and VideoSignals
X. Li, Z. Jiang, and A.N. Willson, Jr.
University of California, Los Angeles, CA
willson@ee.ucla.edu
M4H03
A3203
0073_jqni
Rate-Constrained Adaptive Quantization Scheme for Wavelet
Pyramid Image Coding
J.Q.Ni, K.L. Ho and K.W. Tse
University of Hong Kong, HONG KONG
jqni@hkueee.hku.hk
M4H04
A3204
0541_gschuster
An Optimal Segmentation Encoding Scheme in the Rate Distortion Sense
G. M. Schuster and A. K. Katsaggelos
Northwestern University, Evanston, IL
gschuster@nwu.edu
Monday, 3:30 p.m. -- 5:00 p.m., Room N, Poster Sessions
M4N00
Session Title: Analog Signal Processing -- Analog Sampled-Data Techniques
Chair: F. Maloberti
University of Pavia, Pavia, ITALY
franco@ipvsp4.unipv.it
M4N01
A1211
1468_saman
Comparison of Dithering and Adaptive Schemes used in Sigma-Delta Modulators
S.S. Abeysekera and A. Cantoni
Curtin University of Technology, Perth WA, AUSTRALIA
saman@atri.curtin.edu.au
M4N02
A1212
1495_sli2
A Novel Clock Feed-through Distortion Cancellation Method for SI-Circuits
S. Lindfors and K. Halonen
Helsinki University of Technology , Helsinki, FINLAND
sli@clara.hut.fi
M4N03
A1213
0360_wey6
A High-accuracy CMOS Oversampling Current Sampled/Hold (S/H)
Circuit Using Feedforward Approach
R. Huang and C.-L. Wey
Michigan State University, East Lansing, MI
wey@ee.msu.edu
M4N04
A1214
0616_huang1
A Capacitor-Area Efficient Realization of Sigma-Delta
Modulator-Based FIR/IIR Analog Linear-Phase Filters
Q. Huang
Swiss Federal Institute of Technology, Zurich, SWITZERLAND
huang@iis.ee.ethz.ch
M4N05
A1215
1377_giuse
On the Design of High-Speed High-Resolution Track and Hold
G. Caiulo, C. Fiocchi, U. Gatti and F. Maloberti
Italtel SIT, Milan, ITALY
University of Pavia, Pavia, ITALY
giuse@ipvsp4.unipv.it
M4N06
A1216
0575_r.zeng
A Comparison of Noise-Shaping Clock Generators for
Switched-Capacitor Filters
R. Zeng and P. Hurst
University of California, Davis, CA
zeng@ece.ucdavis.edu
M4N06a
Session Title: Digital Signal Processing -- Speech Processing
Chair: A. Antoniou
University of Victoria, Victoria, BC, CANADA,
andreas@ece.uvic.ca
M4N07
A2211
0268_panos
Wavelet Packet Based Scalable Audio Coding
P.E. Kudumakis and M.B. Sandler
King's College London, London, UK
panos@orion.eee.kcl.ac.uk
M4N08
A2212
0326_wendt
Pitch Determination and Speech Segmentation Using
the Discrete Wavelet Transform
C. Wendt and A.P. Petropulu
Drexel University, Philadelphia, PA
wendtc@cbis.ece.drexel.edu
M4N09
A2213
0708_chitrapu
Linear Prediction Based on Teager-Kaiser Energy Function
and Application to Speech Modeling and Spectral Analysis
P. Chitrapu
Dialogic Corporation, Parsippany, NJ
p.chitrapu@dialogic.com
M4N10
A2214
0829_radha
A Robust Representation of Linear Prediction Coefficients
S.R. Pillai and A. Antoniou
University of Victoria, Victoria, BC, CANADA
radha@ece.uvic.ca
M4N11
A2215
0917_zwang
Cold-Excited Iterated Function Prediction (CEIFP) Speech Coding
at Very Low Bit Rates
Z. Wang
Philips Semiconductors, 811 E. Arques Ave., Sunnyvale, CA 94088-3409
zcwang@scs.philips.com
M4N12
A2216
1167_res
A Wide-Band Speech-Model Process as a Test Signal for
Objective Quality Assessment
M.R. Serafat and U. Heute
University Kiel, Kiel, GERMANY
res@techfak.uni-kiel.d400.de
M4N12a
Session Title: Visual Signal Processing -- Object Detection and Tracking
Chair: Len Bruton
University of Calgary, Calgary, CANADA
bruton@enel.ucalgary.ca
M4N13
A3211
1161_wosnitza
A Scalable VLSI-Architecture for High Resolution Real Time
Object Detection
M. Wosnitza, M. Cavadini, M. Thaler and G. Troester
Swiss Federal Institute of Technology, Zurich, SWITZERLAND
wosnitza@ife.ee.ethz.ch
M4N14
A3212
1304_yamazaki
A Contextual Classification System for Remote Sensing
Using a Multivariate Gaussian MRF Model
T. Yamazaki
Kansai Advanced Research Center, Iwaoka, JAPAN
yamazaki@crl.go.jp
M4N15
A3213
1300_cochran
Nonlinear Filtering Models of Attentive Vision
D. Cochran and R. Martin
Arizona State University, Tempe AZ
Universal Dynamics, Peoria AZ
cochran@asu.edu
M4N16
A3214
1487_ashaw3
Tracking of Multiple Targets Using Pipelined-Adaptive Algorithm
M. Imtiaz and A.K. Shaw
Wright State University, Dayton, OH
ashaw@valhalla.wright.edu
M4N17
A3215
0543_tderryberry
Search-Based Subpixel Tracking
R. Derryberry and J. Dunham
Texas Instruments, Plano, TX
Southern Methodist University, Dallas, TX
tderryberry@ti.com
M4N18
A3216
0250_ahmadi
Affine Point Pattern Matching and its Application to Form Registration
R. Safari, N. Narasimhamurthi, M. Shridhar and M. Ahmadi
University of Windsor, Windsor, ON, CANADA
ahmadi@engn.uwindsor.ca
M4N18a
Network Analysis
Chair:
M4N19
A4211
0325_watanabe
The Legal Firing Sequence Problem of Petri Nets with State Machine Structure
K. Morita and T. Watanabe
Hiroshima University, Higashi-Hiroshima, JAPAN
watanabe@huis.hiroshima-uc.ac.jp
M4N20
A4212
0231_amer-yahia
State Variable Description and Transfer-Functions of a
Class of Continuous Petri Nets
C. Amer-Yahia, N. Zerhouni, A. El-Moudni and M. Ferney
University of Tizi-Ouzou, Tizi-Ouzou, ALGERIA
National School of Engineers, Belfort, FRANCE
M4N21
A4213
0792_wkaichen
On Semi-Indefinite Active n-port Networks
H.-Y. Wang, D.-C. Mu, W.-J. Su and W.-K. Chen
Tianjing University, CHINA
University of Illinois at Chicago, IL
wkchen@eecs.uic.edu
M4N22
A4214
1108_moreira
Filtering and Spectral Processing of 1-D Signals
Using Cellular Neural Networks
O. Moreira-Tamayo, F. Gonzales and J. Pineda de Gyvez
Texas A & M University, College Station, TX
moreira@eesun1.tamu.edu
M4N23
A4215
0331_anto
Circuits as Concurrent Systems: Through a New Approach to the Simulation
A. Monti
Politecnico di Milano, Milano, ITALY
anto@bottani.etec.polimi.it
M4N24
A4216
0960_marinovca
A bounding procedure for voltages in a general network
with distributed and lumped parameters
C.A. Marinov
Polytechnical University of Bucharest, ROMANIA
valentin@vala.elia.pub.ro
marinov@ams.sunysb.edu
M4N24a
Session Title: Power Circuits and Systems -- Simulation and Design of
Power Electronic Circuits
Chair: N. Femia
University di Salerno, Fisciano, ITALY
femia@diiie.unisa.it
M4N25
A5101
0813_shinoda
Idealized Operation of Class DE Frequency Multipliers
K. Shinoda, M. Fujii, M. Matsuo, T. Suetsugu and S. Mori
Keio University, Yokohama, JAPAN
Fukuoka University, Fukuoka, JAPAN
shinoda@mori.elec.keio.ac.jp
M4N26
A5101
0812_bield3
Generating Design Rules for Buck Converter-based Fuzzy Controllers
J. Arias, A. Arias, S. Gomariz and F. Guinjoan
Escola Tecnica Superior d'Enginyers, Barcelona, SPAIN
Polytechnical University of Catalonia, SPAIN
Guinjoan@eel.upc.es
M4N27
A5101
0810_bield
Optimum Dynamic Performance of a Buck Converter
D. Biel, L. Martinez, J. Tenor, Bruno, J. C. Marpinard
Escuela Universitaria Politecnica, Barcelona, SPAIN
Escuela Tecnica Superior de Ingenieria, Tarragona, SPAIN
Laboratoire d'Automatique et d'Architecture des Systemes, Toulouse, FRANCE
Biel@eel.upc.es
M4N28
A5101
1288_desanto3
Calculation of Internally Controlled Switching Instants
in Switched RLC Circuits using Interval Analysis
A. Cirillo and N. Femia
University of Salerno, Salerno, ITALY
desanto@dia.unisa.it
M4N29
A5101
0949_shiwen
A New Analysis Model for Resonant Switching Converter
W. Shi, Z. Hu, R. Cheng and X. Huang
University of Electronic Science and Technology, Chengdu, PR CHINA
M4N30
A5101
0801_vicuna
An Averaged Continuous Model for the Quantum-Series Resonant Converter
M. Castilla, L. Garcia de Vicuna and J. Ordinas
Polytechnical University of Cataluna, SPAIN
mcastilla@eel.upc.es
M4N30a
VLSI Architectures
Chair:
M4N31
A6211
0024_caow
High-Speed Parallel VLSI-Architecture for the (24,12)
Golay Decoder with Optimized Permutation Decoding
W. Cao
Fraunhofer-Institute for Integrated Circuits, Erlangen, GERMANY
caow@iis.fhg.de
M4N32
A6212
0206_cstroud
Design of Signature Registers for Double Error Bit Identification
R. Damarla and C. Stroud
US Army Research Laboratory, Ft. Monmouth, NJ
University of Kentucky, Lexington, KY
damarla@etdl175.arl.mil
M4N33
A6213
0311_kjanik
Synchronous Counterflow Pipeline Processor
K. Janik and S. Lu
Oregon State University, Corvallis, OR
janikk@ece.orst.edu
M4N34
A6214
0350_lai
A Novel Video Signal Processor with Reconfigurable Pipelined Architecture
Y.-K. Lai, L.-G. Chen and M.-C. Chiang
National Taiwan University, Taipei, TAIWAN, ROC
lai@video.ee.ntu.edu.tw
M4N35
A6215
0584_simon
Cordic-Based Architectures for the Efficient Implementation
of Discrete Wavelet Transforms
S. Simon, P. Rieder, C. Schimpfle and Y.A. Nossek
Technical University Munich, Munich, GERMANY
svsi@nws.e-technik.tu-muenchen.de
M4N36
A6216
1169_montalvo_parhi
Radix-2 Over-Redundant Digit-Set Converters
L. Montalvo and K.K. Parhi
University of Minnesota, Minneapolis, MN
parhi@ee.umn.edu
montalvo@ee.umn.edu
M4N36a
Session Title: Neural Systems and Applications -- Neural Technologies
for Prediction, Identification and Control
Chair: V. Piuri
Politecnico di Milano, Milano, ITALY
piuri@elet.polimi.it
M4N37
A7211
2901
Identification of nonlinear dynamic systems with
recurrent neural networks trained by extended Kalman filter methods
Stephan Straub
Technical Univ. of Munich, Munich, GERMANY
straub@nws.e-technik.tu-muenchen.de
M4N38
A7212
2902
Monitoring and modeling dynamic processes using
hierarchical self-organizing maps
Olli Simula
Helsinki Univ. of Technology, Helsinki, FINLAND
olli.simula@hut.fi
M4N39
A7213
2903
A simulation environment for behavioral design of
neural networks for prediction and control
V. Piuri
Politecnico di Milano, Milano, ITALY
piuri@elet.polimi.it
piuri@pine.ece.utexas.edu
M4N40
A7214
2904
A neural ensemble for speech recognition
Eros Pasero
Politecnico di Torino, Torino, ITALY
pasero@polito.it
M4N41
A7215
2905
Attentional mode neural network: a new approach for
real-time self-learning
P. M. Engel
Universidade Federal do Rio Grande do Sui, BRAZIL
engel@inf.ufrgs.br
M4N42
A7216
2906
Rapid learning and dynamic stepwise updating for
forecasting time series using a flat neural network
D. L. P. Chen and C-I. H. Chen
Wright State University, Dayton, OH
cihchen@valhalla.cs.wright.edu
M4N42a
Computer-Aided Design
Chair:
M4N43
A8211
0019_bisdouni
Modeling the CMOS Short-Circuit Power Dissipation
L. Bisdounis, S. Nikolaidis, O. Koufopavlou and C. E. Goutis
VLSI Design Laboratory, University of Patras, Patras, GREECE
bisdouni@ee.upatras.gr
M4N44
A8212
0807_manli
Computing Parametric Yield Using Adaptive Statistical Piecewise Linear Models
M. Li and L. Milor
University of Maryland, College Park, MD
University of California, Berkeley, CA
manli@radon.eecs.berkeley.edu
M4N45
A8213
1329_kywu_genetic
A Parallel Optimal Statistical Design Method based on
Genetic Algorithm
K.Y. Wu,Y. Shen, R.M.M. Chen and A.K.M. Wu
City University of Hong Kong, HONG KONG
kywu@cpeelgx03.cityu.edu.hk
M4N46
A8214
1355_nanping
Parameterized Layout Synthesis, SPICE Simulation and CAD
Visualization for MEMS
N.R. Lo, E. Berg, S. Quakkelaar, M. Tachiki, J. Simon,
H. Lee and K.S.J. Pister
University of California, Los Angeles, CA
nanping@ee.ucla.edu
M4N47
A8215
1400_tto
A Novel Sensitivity Analysis Technique for VLSI Statistical Design
H.-Y. To, H. Su and M. Ismail
Intel Corporation, Folsom, CA
Imperial College, London, UK
Ohio State University, Columbus, OH
tto@mcd.intel.com
M4N48
A8216
1401_lamnan
PECS: A Peak Current and Power Simulator for CMOS Combinational Circuits
K.N. Lam and S. Devadas
CompCore Multimedia, Inc., Santa Clara, CA
lamnan@compcore.com
M4N49
0974_machado
An Analytical Lumped-Parameter 3D Cochlear Model and Architecture
for Cochlear Signal Processing in VLSI
G.A.S. Machado and C. Toumazou
Imperial College, London, UK
g.machado@ic.ac.uk
Monday, 5:30 p.m. -- 6:30 p.m., Ballroom
FORUM on CAS Design: What Do We Mean and What Should We Be Doing?
Organizers and Chairs:
Rui J. P. de Figueiredo, University of California, Irvine
Bing Sheu, University of Southern California, Los Angeles, CA
Panelists:
A. Fettweis, University of Notre Dame, Notre Dame, IN
T. Wiswanathan, Texas Instruments, TX
S. Kang, University of Illinois, Urbana, IL
J. Choma, University of Southern California, Los Angeles, CA
Tuesday, 8:30 a.m. -- 10:00 a.m., Room A
T1A00
Session Title: Analog Signal Processing -- Analog Filters I
Chair: Christopher Toumazou
Imperial College of Science, Technology and Medicine London, UK
chris@ic.ac.uk
T1A01
A1301
0082_1serrano
MOSFET-C Filter Design Based on Impedances Simulation
L. Serrano and A. Carlosena
University Publica de Navarra, Pamplona, NA, SPAIN
lserrano@tsc.upna.es
T1A02
A1302
0333_wada
Automatic Tuning System for High-Frequency Integrated
Continuous-Time Filters
K. Wada, S. Takagi and N. Fujii
Tokyo Institute of Technology, Meguro-ku, Tokyo, JAPAN
wada@ss.titech.ac.jp
T1A03
A1303
1406_nairn
Tunable Capacitors for Digital CMOS Compatible High-Frequency
Analog Filters
G. Allbutt and D.G. Nairn
Queen's University, Kingston, ON, CANADA
nairn@eleceng.queensu.ca
T1A04
A1304
0343_tvoo
Efficient Tunable Continuous-Time Integrated Current-Mode Filter Designs
T. Voo and C. Toumazou
Imperial College of Science, Technology and Medicine London, UK
t.voo@ic.ac.uk
Tuesday, 8:30 a.m. -- 10:00 a.m., Room B
T1B00
Session Title: Neural Network Applications -- Fundamentals of Neural Networks I
Chair: R.J.P. de Figueiredo
University of California, Irvine, CA
rui@uci.edu
T1B01
A7301
1701
The OI, OMNI, and OSMAN networks as best approximations of
non-linear systems under training data contraints
Rui J.P. de Figueiredo
rui@uci.edu
T1B02
A7302
1707
The CNN Universal Machine--A Stored Program Supercomputer
on a Chip
Bertram Shi and Leon O. Chua
University of California, Berkeley, CA
eebert@ee.ust.hk
T1B03
A7303
1702
Stabliity Analysis of Artificial Neural Networks with Multiple Delays
Anthony N. Michel, Hui Ye, and Kaining Wang
University of Notre Dame, Notre Dame, IN
Anthony.N.Michel.1@nd.edu
T1B04
A7304
1703
Tensor product neural networks and approximation of dyamical systems
Anjit Dingankar, Irwin W. Sandberg
University of Texas, Austin, TX
sandberg@telesys35.ots.utexas.edu
Tuesday, 8:30 a.m. -- 10:00 a.m., Room C
T1C00
Session Title: Computer-Aided Design -- Meta-Heuristics in VLSI Layout
Chair: A.B. Kahng
University of California, Los Angeles, CA
abk@cs.ucla.edu
T1C01
A8301
2002
On clustered kick moves for iterated-descent netlist partitioning
Fukunaga, Huang and Kahng
University of California, Los Angeles, CA
abk@cs.ucla.edu
T1C02
A8302
2003
Design space exploration using the genetic algorithm
Esbensen and Kuh
University of California, Berkeley, CA
abk@cs.ucla.edu
T1C03
A8303
2004
A performance-driven placement technique based on a
new budgeting criterion
Tellez, Knol and Sarrafzadeh
Northwestern University, Chicago, IL
abk@cs.ucla.edu
T1C04
A8304
2006
A Parallel Genetic Algorithm for Two Detailed Routing Problems
J. Lienig
University of Virginia, Charlottesville, VA
jens@cs.virginia.edu
Tuesday, 8:30 a.m. -- 10:00 a.m., Room D
T1D00
Session Title: Digital Signal Processing -- Multirate and Filter Banks I
Chair: T. Nguyen
University of Wisconsin, Madison, WI
nguyen@ece.wisc.edu
T1D01
A2301
0277_vukadino
A Study of Adaptive Intersubband Tap Assignment Algorithms
from a Psychoacoustic Point of View
M. Vukadinovic and T. Aboulnasr
University of Ottawa, Ottawa, ON, CANADA
vukadino@trix.genie.uottawa.ca
T1D02
A2302
0348_cww
On Fault-Tolerant FFT Butterfly Network Design
S.-K. Lu, S.-Y. Kuo and C.-W. Wu
National Taiwan University, Taipei, TAIWAN, ROC
National Tsing Hua University, Hsinchu, TAIWAN, ROC
c.wu@ieee.org
T1D03
A2303
0644_ppvnath
Two-Dimensional Linear Phase Cosine Modulated Filter Banks
Y. Lin and P.P. Vaidyanathan
California Institute of Technology, Pasadena, CA
ppvnath@systems.caltech.edu
T1D04
A2304
1382_zsijerci
Factorizations of IIR Biorthogonal Filter Banks Based
on Generalized Bezout Identity
Z. Sijercic and G. Agarwal
University of Illinois at Chicago, Chicago, IL
sijercic@cs.colostate.edu
Tuesday, 8:30 a.m. -- 10:00 a.m., Room E
T1E00
Session Title: Power Circuits & Systems -- Applications of
Fuzzy Logic to Power Systems
Chair: H. Mori
Meiji University, Japan
hmori@isc.meiji.ac.jp
T1E01
A5101
2601
Fuzzy Logic Switching of FACTS Devices for Stability Enhancement
Takashi Hiyama, Hidemi Kihara, Hajime Miyauchi and Thomas H. Ortmeyer
Kumamoto University, JAPAN and Clarkson University, USA
hiyama@eecs.kumamoto-u.ac.jp
ortmeyer@sun.soe.clarkson.edu
T1E02
A5101
2602
Stability analysis methods of fuzzy logic controls for power systems
Kevin Tomsovic
Washington State University
tomsovic@eecs.wsu.edu
T1E03
A5101
2603
Reliability evauation of generation/transmission power systems
including fuzzy data
J. Tome Saraiva
Universidade do Porto, Porto, PORTUGAL
jsaraiva@porto.inescn.pt
T1E04
A5101
2604
Design of robust transformer fault diagnosis system using
evolutionary fuzzy logic
Y. C. Huang, H. T. Yang and C. L. Huang
Chung-Yuan University, Chung-Li, TAIWAN
htyang@mail.ncku.edu.tw
T1E05
A5101
2605
Application of a fuzzy set method in distribution system
fault location
Edwin Liu and Weili Zhong
Pacific Gas & Electric Co., San Francisco, CA
hmori@isc.meiji.ac.jp
T1E06
A5101
2606
Fuzzy inference based identification of load characteristics
Hiroyuki Mori
Meiji University, Kawasaki, JAPAN
hmori@isc.meiji.ac.jp
Tuesday, 8:30 a.m. -- 10:00 a.m., Room F
T1F00
Session Title: Nonlinear Circuits & Systems -- Arrays of Coupled
Nonlinear Dynamical Systems I
Chairs: M. Hasler and P. Thiran
Swiss Federal Institute of Technology, Lausanne, SWITZERLAND
Martin.Hasler@circ.de.epfl.ch
thiran@circhp.epfl.ch
T1F01
A4301
1801
Complicated and Computational Dynamics of Spatio-temporal Neurochaos
K. Aihara
University of Tokyo, Tokyo, JAPAN
aihara@sat.t.u-tokyo.ac.jp
T1F02 --WITHDRAWN
A4302
1802
Study of noise influence on self-organisation phenomena in chaotic neural networks
M.J. Ogorzalek, Z. Galias and A. Cichocki
University of Mining and Metallurgy, Krakow, POLAND
maciej@zet.agh.edu.pl
T1F03
A4303
1803
On Synchronization Phenomena in Coupled Chaotic Circuits Networks
Y. Nishio, A. Ushida
Tokushima University, JAPAN
nishio@ee.tokushima-u.ac.jp
T1F04
A4304
1804
Traveling Wave Solutions for Spatially Discrete Bistable
Reaction-Diffusion Equations
Erik S. Van Vleck
Colorado School of Mines
erikvv@poincare.mines.edu
Tuesday, 8:30 a.m. -- 10:00 a.m., Room G
T1G00
Session Title: VLSI Systems and Applications -- VLSI Cicruits
for Wireless Applications I
Chair: B. H. Leung
University of Waterloo, Waterloo, Canada
bleung@sun14.vlsi.uwaterloo.ca
T1G01
A6301
2101
A Direct-Conversion Transceiver Chip Set for 900 MHz (ISM Band)
Spread-Spectrum Digital Cordless Telephone
J. L. Tham, c. Hull, A. Ali, F. Carr, R. Chu, J. Walley
and I. Koullias
Rockwell International
jtham@atlas.nb.rockwell.com
T1G02
A6302
2102
Low Voltage Circuit Solutions for a Single Chip 2 GHz
Transmitter/Receiver for Mobile Telecommunication
V. Porra, K. Halonen, K. Koli, M. Paakkonen, S. Siilasto,
E. Tiiliharju, P. Tolonen and T. Wahlroos
Helsinki University of Technology
veikko@daisy.hut.fi
T1G03
A6303
2103
RF and Microwave Building Blocks in a Standard BiCMOS Technology
M. Soyuer, J. N. Burghartz, K. A. Jenkins, H.A. Ainspan and F. J. Canora
IBM T. J. Watson Research Center
soyuer@watson.ibm.com
T1G04
A6304
2104
Receiver RF Design Considerations for Wireless Communications Systems
K. Hansen and A. Nogueras
Motorola
ken_hansen-ekh002@email.mot.com
T1G05
A6305
2105
A Hardware-Efficient D/A Converter for Direct Digital Synthesis
H. T. Jensen and I. Galton
University of California, Irvine
galton@ece.uci.edu
Tuesday, 8:30 a.m. -- 10:00 a.m., Room H
T1H00
Session Title: Digital Signal Processing -- Blind Signal Processing I
Chair: R. Liu
University of Notre Dame, Notre Dame, IN
liu.1@nd.edu
T1H01
A3301
2201
An overview of blind signal processing
Ruey-wen Liu
liu.1@nd.edu
T1H02
A3302
2202
Performance and implementation of invariant source separation algorithms
Jean-Francois Cardoso
ENST/CNRS, Paris, FRANCE
cardoso@sig.enst.fr
liu.1@nd.edu
T1H03
A3303
2203
Blind channel identification with applications to wireless communication
Lang Tong
liu.1@nd.edu
T1H04
A3304
2204
Independent component analysis, a survey of some algebraic methods
J. F. Cardoso and Pierre Comon
ENST/CNRS, Paris, FRANCE
cardoso@sig.enst.fr
University of Nice, Nice, FRANCE
pierre@thym.unice.fr
Tuesday, 8:30 a.m. -- 10:00 a.m., Room N, Poster Sessions
T1N00
Session Title: Analog Signal Processing -- Analog Techniques
Chair: Steve DeWeerth
Georgia Institute of Technology, Atlanta, GA
steve.deweerth@ece.gatech.edu
T1N01
A1311
0842_muhamada
A Fuzzy Logic System for Analog Fault Diagnosis
M. Abdulghafour and M. El-Gamal
U.A.E. University, Al-Ain, U.A.E.
muhamad@nyx.uaeu.ac.ae
T1N02
A1312
0695_op
Worst-Case Parameters Derived from Device Physics
O. Prigge, M. Miura-Mattausch, D. Savignac and U. Feldmann
Siemens AG, Munich, GERMANY
op@pauli.zfe.siemens.de
T1N03
A1313
1208_denise
Rank-Order Filtering in Analog VLSI
D.M. Wilson and S.P. DeWeerth
Georgia Institute of Technology, Atlanta, GA
denise@ece.gatech.edu
T1N04
A1314
0973_khhadidi
A Highly Linear Cascode-Driver CMOS Source-Follower Buffer
K. Hadidi and A. Khoei
Urmia University, Urmia, IRAN
FAX--9844130526
T1N05
A1315
0779_sitthichai
Automatic Circuit Simplification for Meaningful Symbolic
Analysis using the Genetic Algorithm
S. Pookaiyaudom and S. Jantarang
Mahanakron University of Technology, Bangkok, THAILAND
sitthichai@mut.ac.th
T1N06
A1316
1128_sigbjorn
Frequency Analysis in Micropower Analog CMOS
S. Naess and T.S. Lande
University of Oslo, Oslo, NORWAY
sigbjorn@ifi.uio.no
T1N06a
Session Title: Digital Signal Processing -- Nonlinear DSP II
Chair: Y. H. Lee
Korea Advanced Institute of Science and Technology, Taejon, KOREA
yohlee@eekaist.kaist.ac.kr
T1N07
A2311
0069_isao
A New Adaptive Damped Convergence Factor Algorithm
with a Bias Term
I. Nakanishi, Y. Itoh and Y. Fukui
Tottori University, Tottori, JAPAN
isao@fed.tottori-u.ac.jp
T1N08
A2312
0117_rsucher
A Self-Organizing Nonlinear Filter Based on Fuzzy Clustering
R. Sucher
Technical University of Vienna, AUSTRIA
rsucher@email.tuwien.ac.at
T1N09
A2313
0286_spetsa2
Hierarchical Frequency Grid Management for Arbitrary Response
FWL IIR Filter Design using a Genetic Algorithm
T. Arslan and D.H. Horrocks
University of Wales, College of Cardiff, Cardiff, UK
arslan@cardiff.ac.uk
T1N10
A2314
0795_ruikang
Use of Fractals and Median Type Filters in Color Texture Segmentation
L. Song, R. Yang, K. Saarinen and M. Gabbouj
Tampere University of Technology, Tampere, FINLAND
ruikang.yang@research.nokia.com
T1N11
A2315
1252_mapeko
Optimal Soft Morphological Filtering under Breakdown Probability Constraints
P. Koivisto, H. Huttunen and P. Kuosmanen
Tampere University of Technology, Tampere, FINLAND
mapeko@uta.fi
T1N12
A2316
1409_najim
Order Statistics Fast Kalman Filter
D. Ottaviani, R. Settineri and M. Najim
Equipe Signal et Image, Enserb, FRANCE
najim@goelette.tsi.u-bordeaux.fr
T1N12a
Session Title: Digital Signal Processing -- DSP Computation
Chair: T. Laakso
University of Westminster, London, UK
timol@westminster.ac.uk
T1N13
A3311
0030_corral
Minimax Algorithm for Matrix Inversion
C. A. Corral
Scientific-Atlanta, Atlanta, GA
tino.corral@sciatl.com
T1N14
A3312
0049_enkclo
Reconstructing Randomly Sampled Signals by the FFT
K. C. Lo and A. Purvis
The Hong Kong Polytechnic University, Kowloon, HONG KONG
University of Durham, Durham, UK
enkclo@hkpucc.polyu.edu.hk
T1N15
A3313
0232_djennoune
Approximation of the Sampled-Data Lnear Quadratic Control
Systems by Bilinear Transformation
S. Djennoune, A. El Moudni, N. Zerhouni and M. Ferney
National School of Engineers, Belfort, FRANCE
University of Tizi-Ouzou, Tizi-Ouzou, ALGERIA
T1N16
A3314
0569_whf
A Signal Enhanced State Space Approach for the Estimation
of Two-Dimensional Frequencies
Y. Chu, W.-H. Fang and M.-H. Huang
National Taiwan Institute of Technology, Taipei, TAIWAN, ROC
whf@et.ntit.edu.tw
T1N17
A3315
0572_hartwig
Roundoff Noise Analysis on the Basis of an Improved
Floating Point Error Model
F. Hartwig and A. Lacroix
University of Frankfurt, Frankfurt, GERMANY
Pietsch@iap.uni-frankfurt.de
T1N18
1550
Bifurcational Communication With Novel Chaotic Transistors Circuits
Cong-Khu Pham
Sophia University, Tokyo, JAPAN
pham@saturn.ee.sophia.ac.jp
T1N19
A4311
2802
PLL Demodulation of Chaotic Signals from Periodically
Forced Information Transmission Systems
Andreas Abel, Marco Gotz and Wolfgang Schwarz
Technical Universitat Dresden, Dresden, GERMANY
maciej@fractal.zet.agh.edu.pl
abel@iee1.et.tu-dresden.de
gchen@uh.edu
T1N20
A4312
2817
A stochastic approach to spread spectrum communication
Joerg Schweizer
maciej@fractal.zet.agh.edu.pl
T1N21
A4313
2801
Secure communication system using chaos via DSP implementation
Hiroyuki Kamata, Tetsuro Endo and Yoshihisa Ishida
Meiji University, Kawasaki, JAPAN
maciej@fractal.zet.agh.edu.pl
gchen@uh.edu
T1N22
A4314
2807
Generalized synchronization of Chaos
L. Kocarev, U. Parlitz, kT. Stojanovski and L. Panovski
Sts. Cyril and Methodius University, Skopje, MACEDONIA
lkocarev@cerera.etf.ukim.edu.mk
maciej@fractal.zet.agh.edu.pl
gchen@uh.edu
T1N23
A4315
2811
A feedback chaos controller: Theory and implementation
Z. Galias, C.A. Murphy, M.P. Kennedy and M.J. Ogorzalek
maciej@fractal.zet.agh.edu.pl
T1N24
A4316
2805
Synchronization of chaos from a simple RC OTA chaotic
circuit with dependent switched capacitor
Kunihiko Mitsubori and Toshimichi Saito
Hosei University, Tokyo, JAPAN
mitsu@toshi.ee.hosei.ac.jp
saito@toshi.ee.hosei.ac.jp
T1N25
1563
Optimal Algorithms for Max / Min Filtering
Dinu Coltuc
Politehnica University of Bucuresti, Bucuresti, ROMANIA
dcoltuc@paul.dsp.pub.ro
T1N25a
Session Title: Power Circuits and Systems -- Power Electronic Devices
Chair: F. Guinjoan
Polytechnical University of Catalonia, SPAIN
Guinjoan@eel.upc.es
T1N26
A5101
1207_wendu
Accurate Diode Forward and Reverse Recovery Model
using Asymptotic Waveform Evaluation Techniques
W. Beyene and J. Schutt-Aine
University of Illinois, Urbana-Champaign, IL
wendu@decwa.ece.uiuc.edu
T1N27
A5101
0780_speciale
A New DC Model for FIve-Terminals Bipolar Devices Used
in Smart-Power ICs
N. Speciale, G. Onofri, S. Graffi, G. Masetti, S. Palara and G. Privitera
University of Bologna, ITALY
speciale@deis05.cineca.it
T1N28
A5101
0528_soowon1
1.2um Non-epi CMOS Smart Power IC with Four H-bridge
Motor Drivers for Portable Applications
S. Kim, B. Kim, C. Kim, S. Han, H. Park and H. Park
Korea University, Seoul, KOREA
Hyundai Electronics Industries Co. Ltd., Kyungki-do, KOREA
soowon@asic02.korea.ac.kr
T1N29
A5101
0415_jry
Principle of CMOS Circuit Power-Delay Optimization
with Transistor Sizing
J. Yuan and C. Svensson
Linkoping University, Linkoping, SWEDEN
jry@ifm.liu.se
T1N30
A6311
1005_adler
Delay and Power Expressions for a CMOS Inverter Driving
a Resistive-Capacitive Load
V. Adler and E. G. Friedman
University of Rochester, Rochester, NY
adler@ee.rochester.edu
T1N31
A6312
0062_hillam1
Statistical Estimation of Short-Circuit Power in VLSI Circuits
A. Hill and S. Kang
University of Illinois at Urbana-Champaign, Urbana, IL
hillam@uivlsi.csl.uiuc.edu
T1N32 --WITHDRAWN
A6313
1301_kornegay
High-Speed Switching Circuits for Ultrafast Optical Processing
L. Chiou and K. Kornegay
Purdue University, West Lafayette, IN
kornegay@yara.ecn.purdue.edu
T1N33
A6314
1021_bernabe
Systematic CMOS Transistor Mismatch Characterization
T. Serrano-Gotarredona, B. Linares-Barranco, and J. L. Huertas
National Microelectronics Center, Sevilla, SPAIN
bernabe@cnm.us.es
T1N34
A6315
0092_mkl1
Influence of Machine Model ESD Stress on the Failure Threshholds
of CMOS Protection Circuit Elements
M. Lee
Sharp Microelectronics Technology, Inc., Camas, WA
mkl@sharpwa.com
T1N35
A6316
0304_reber
Benefits of Vertically Stacked Integrated Circuits for
Sequential Logic
M. Reber
University of Kaiserslautern, GERMANY
reber@rhrk.uni-kl.de
T1N36
1555
Clock-and Data-Recovery IC with Demultiplexer for
a 2.5 Gb/s ATM Physical Layer Controller
F. Hansen and C.A.T. Salama
Technical University of Denmark, Lyngby, Denmark
University of Toronto, Ontario, Canada
fh@emi.dtu.dk
T1N37
1559
A Resonant Clock Driver for Two-Phase, Almost Non-Overlapping Clocks
W. C. Athas and L.J. Svensson
USC/Infor. Sciences Institute, Marina del Rey CA, USA
athas@isi.edu
T1N37a
Session Title: Neural Systems and Applications -- Hardware Implementation I
Chair: Majid Ahmadi
University of Windsor, ON, CANADA
ahmadi@engn.uwindsor.ca
T1N38
A7311
0324_han
A Resistorless Small Area, Lowpower CMOS Four-quadrant Multipier
G. Han and E. Sanchez-Sinencio
Texas A&M University, College Station, TX
han8613@amesp01.tamu.edu
T1N39
A7312
0285_harris
A Continuous-Time Analog Circuit for Computing Time Delays Between Signals
C. Pu and J.G. Harris
University of Florida, Gainesville, FL
harris@knicks.ee.ufl.edu
T1N40
A7313
0647_bdliu
Modular Current-Mode Multiple Input Minimum Circuit for
Fuzzy Logic Controllers
C.Y. Huang, C.J. Wang and B.D. Liu
National Cheng Kung University, Taiwan, TAIWAN, ROC
bdliu@cad8.cme.ncku.edu.tw
T1N41
A7314
0006_akers2
Analog VLSI Implementations of Receptive Field Profiles
Found in Visual Cortical Neurons
L. Theogarajan and L.A. Akers
Arizona State University, Tempe, AZ
lakers@asu.edu
T1N42
A7315
0315_hsng
Current-mode Optimization Circuits for Minimax Path Problems
H. S. Ng and K. P. Lam
The Chinese University of Hong Kong, Shatin, N.T., HONG KONG
hsng@se.cuhk.hk
T1N43
A7316
0874_wawryn1
Low power VLSI neuron cells for artificial neural networks
K. Wawryn and B. Strzeszewski
Technical University of Koszalin, POLAND
wawryn@gumbeers.elka.pg.gda.pl
T1N44
A8311
0290_bapi2
Data Parallel Sequential Circuit Fault Simulation
M. B. Amin and B. Vinnakota
University of Minnesota, Minneapolis, MN
bapi@ee.umn.edu
T1N45
A8312
0301_uebel2
A Timing Analysis Tool for VLSI CMOS Synchronous Circuits
L. F. Uebel and S. Bampi
CPGCC - Informatics Institute UFRGS, Porto Alegre, BRAZIL
uebel@inf.ufrgs.br
T1N46
A8313
0337_sachin
Efficient Calculation of All-Pairs Input-to-Output Delays
in Synchronous Sequential Circuits
S.S. Sapatnekar
Iowa State University, Ames, IA
sachin@iastate.edu
T1N47
A8314
0904_wawryn2
Automated fault diagnosis based on multilevel formal
language knowledge representation
K. Wawryn and J. Drabarek
Technical University of Koszalin, Koszalin, POLAND
wawryn@gumbeers.elka.pg.gda.pl
T1N48
A8315
1066_jkong
Timing Verification for the Non-Periodic Gated Clocking
H. Kim, E. Chung, J. Kong and S. Lee
CAE, Memory Division Semiconductor Business, Samsung Electronics, KOREA
jkong@semigw.semi.samsung.co.kr
T1N49
A8316
1227_jsousa
On Structural Diagnosis for Interconnects
J.T. Sousa, T. Shen and P.Y.K. Cheung
Imperial College of Science, Technology and Medicine, London, UK
j.sousa@ic.ac.uk
Tuesday, 10:30 a.m. - 12:00 p.m., Room A
T2A00
Session Title: Analog Signal Processing -- Analog Filters II
Chair: Christian C. Enz
T2A01
A1401
0353_yang
Design of Low-Power & Low-Voltage Log-Domain Filters
F. Yang and C.C. Enz
Swiss Federal Institute of Technology, Lausanne, SWITZERLAND
yang@leghp1.epfl.ch
T2A02
A1402
0800_tsividis
Current-Mode Filters using Syllabic Companding
Y. Tsividis and D. Li
Columbia University, New York, NY
tsividis@elab.columbia.edu
T2A03
A1403
0355_punzen
A New 1.2V BiCMOS Log-Domain Integrator for Companding
Current-Mode Filters
M. Punzenberger and C. Enz
Swiss Federal Institute of Technology, Lausanne, SWITZERLAND
punzen@legsun4.epfl.ch
T2A04
A1404
0604_ksyoon2
Design of a 3V-50MHz Analog CMOS Current-Mode NRL Filter
J.S. Hyun and K.S. Yoon
Inha University, Incheon, KOREA
ksyoon@dragon.inha.ac.kr
Tuesday, 10:30 a.m. - 12:00 p.m., Room B
T2B00
Session Title: Neural Systems and Applications -- Multi-Valued Neural Networks
Chair: R.J.P. de Figueiredo
University of California, Irvine, CA
rui@uci.edu
T2B01
A7401
1704
Tracking capabilities of single-layer threshold networks
when confronted with drift and random noise
Xiaodong Tian and Anthony Kuh
University of Hawaii, Honolulu, HI
kuh@spectra.eng.hawaii.edu
T2B02
A7402
1705
Comparison of Learning Algorithms for Feedforward Multilayer Neural Nets
Peter Nachbar, Andreas J. Schuler and Josef A. Nossek
Technical University of Munich, Munich, GERMANY
josef.a.nossek@nws.e-technik.tu-muenchen.de
T2B03
A7403
1706
An N-Limit Cycle Artificial Neuron for Multi-Valued ANNS
Ta-Wei-YAng, Nittaya Pimchaiping, R. W.Newcomb, and RJP de Figueiredo
University of Maryland, College Park, MD
newcomb@eng.umd.edu
T2B04
A7404
0400_jmzurda3
Layer Interactions in a Multivalued Neural Associative Memory
S. Jankowski, A. Lozowski and J.M. Zurada
Warsaw University of Technology, Warsaw, POLAND
University of Louisville, Louisville, KY
jmzura02@starbase.spd.louisville.edu
Tuesday, 10:30 a.m. - 12:00 p.m., Room C
T2C00
Session Title: Computer-Aided Design -- Modeling and Simulation
Chair: Steve Kang
University of Illinois, Urbana, IL, USA
kang@uivlsi.csl.uiuc.edu
T2C01
A8401
1336_luk_wing
Waveform Krylov Subspace Methods for Tightly Coupled Systems
W. S. Luk and O. Wing
Chinese University of Hong Hong, HONG KONG
luk036@cs.cuhk.hk
T2C02
A8402
1041_elias
Efficient Moments Extraction of Large Inductively Coupled
Interconnection Networks
P.J.H. Elias and N.P. van der Meijs
Delft University of Technology, Delft, NETHERLANDS
elias@cas.et.tudelft.nl
T2C03
A8403
0713_haowei
Minimizing Chip-Level Simultaneous Switching Noise for
High-Performance Microprocessor Design
H.H. Chen
Thomas J. Watson Research Center, Yorktown Heights, NY
haowei@watson.ibm.com
T2C04
A8404
0522_du2
Derivation of Signal Flow Directions and Synchronizers for
Switch-Level Timing Analysis
J. Kim, J. Lee and D.H.C. Du
University of MInnesota, Minneapolis, MN
du@cs.umn.edu
jhkim@cadence.com
Tuesday, 10:30 a.m. - 12:00 p.m., Room D
T2D00
Session Title: Digital Signal Processing -- Transforms and
Transform Coding I
Chair: M. Sandler
King's College London, London, UK
m.sandler@kcl.ac.uk
T2D01
A2401
0135_victor2
Block multitransform coding of non-stationary signals
V. E. DeBrunner, W. Lou and J. Thripuraneni
University of Oklahoma, Norman, OK
vdebrunn@uoknor.edu
T2D02
A2402
0200_reza
Efficient Variable-Length_Coding Under an Assigned Maximum
Code-Length Constraint
R. Hashemian
Northern Illinois University, Dekalb IL
reza@ceet.niu.edu
T2D03
A2403
1155_vfranque
Subband Coding of Images Using the Eigen Designed Quadrature
Mirror Filters
V. T. Franques
University of South Florida, Tampa, FL
VFRANQUE@SUNFLASH.ENG.USF.EDU
victoria@tiger.eglin.af.mil
T2D04
A2404
1247_mikaelr
New Approaches to High Speed Huffman Decoding
M. Karlsson and R.L. Wanhammar
Linkopings Univ, Linkoping, SWEDEN
mikaelr@isy.liu.se
Tuesday, 10:30 a.m. - 12:00 p.m., Room E
T2E00
Session Title: VLSI Systems and Applications -- Logic/Memory Circuits
Chair: Ramalingam Sridhar
SUNY, Buffalo, NY
T2E01
A5401
0075_kim2
Assessing Merged DRAM/Logic Technology
Y.Kim and T. Chen
Hewlett Packard Company, Fort Collins, CO
Colorado State University, Fort Collins, CO
ybk@hpesybk.fc.hp.com
T2E02
A5402
0299_rtekumal
Delay Testable Non-Scan Sequential Circuits with Clock Suppression
R. Tekumalla and P.R. Menon
University of Massachusetts, Amherst, MA
menon@ohm.ecs.umass.edu
T2E03
A5403
0074_kim1
Clock Skew on DRAM/Logic Merged Technology Based Systems
Y.Kim and T. Chen
Hewlett Packard Company, Fort Collins, CO
Colorado State University, Fort Collins, CO
ybk@hpesybk.fc.hp.com
T2E04
A5404
1096_parhi2
Synthesis of Low-Area Data Format Converters
M. Majumdar and K.K. Parhi
University of Minnesota, Minneapolis, MN
parhi@ee.umn.edu
Tuesday, 10:30 a.m. - 12:00 p.m., Room F
T2F00
Session Title: Nonlinear Circuits & Systems -- Arrays of Coupled
Nonlinear Dynamical Systems II
Chairs: M. Hasler and P. Thiran
Swiss Federal Institute of Technology, Lausanne, SWITZERLAND
Martin.Hasler@circ.de.epfl.ch
thiran@circhp.epfl.ch
T2F01
A4401
1805
The Synergetics approach to image processing in Cellular Neural Networks
Kenneth R. Crounse and Leon O. Chua
University of California, Berkeley, CA
crounse@fred.eecs.berkeley.edu
T2F02
A4402
1806
An Electronic Real-Time Model of One-Dimensional Discontinuous
Conduction of the Cardiac Impulse Realized with Chua's Circuits
A.P. Munuzuri, V. Perez-Munuzuri, M. Gomez-Gesteira, M. de Castro,
I.P. Marino, E. Hofer and V. Perez-Villar
University of Santiago di Compostela, SPAIN
University Karl Franzens, Graz, AUSTRIA
uscfmvpm@cesga.es
T2F03
A4403
1807
Dynamics of Coupled Nonlinear Oscillators:
from Relaxation Oscillators to Neurons
Paul S. Linsay, Andrew Cummings, Adam A. Brailove, Chris Wilson,
Paolo Gaudiano and Andrzej Przybyszewshi
M.I.T., Cambridge, MA
Boston University, Boston, MA
linsay@pfc.mit.edu
T2F04
A4404
1808
Spatio-temporal patterns in Cellular Neural Networks
Patrick Thiran, Gianluca Setti and Kenneth R. Crounse
Swiss Federal Inst. of Technology, Lausanne, SWITZERLAND
University of Bologna, Bologna, ITALY
University of California, Berkeley, CA
gsetti@deis.unibo.it
Tuesday, 10:30 a.m. - 12:00 p.m., Room G
T2G00
Session Title: VLSI Systems and Applications -- VLSI Cicruits
for Wireless Applications II
Chair: B. H. Leung
University of Waterloo, Waterloo, Canada
bleung@sun14.vlsi.uwaterloo.ca
T2G01
A6416
0369_madhavan
A Novel High Speed Low Skew Clock Distribution Scheme in
0.8 micron CMOS
B. Madhavan, B. Sano and A. F. J. Levi
University of Southern California, Los Angeles, CA
madhavan@marco.usc.edu
T2G02
A6414
0087_marak
Data-Controlled Delays in the Asynchronous Design
Victor I.Varshavsky, Vyacheslav B.Marakhovsky and Masayuki Tsukisaka
University of Aizu-Wakamatsu, Fukushima, JAPAN
marak@u-aizu.ac.jp
T2G03
A6413
1324_rsridhar
Speed and Power Comparison of CMOS Wave Pipelined Systems
R. Sridhar, A. Martinez-Smith and B. McGee
State University of New York, Buffalo, NY
rsridhar@eng.buffalo.edu
T2G04
A5411
0422_vschindl
Prototype Testing of High Speed CMOS Digital Circuits
V. Schindler
Graz University of Technology, Graz, AUSTRIA
vschindl@iaik.tu-graz.ac.at
Tuesday, 10:30 a.m. - 12:00 p.m., Room H
T2H00
Session Title: Digital Signal Processing -- Blind Signal Processing II
Chair: R. Liu
University of Notre Dame, Notre Dame, IN
liu.1@nd.edu
T2H01
A2011
2205
A unified algorithm to blind separation of independent sources
Jie Zhu, Xi-Ren Cao and Ming L. Liou
EECAO@usthk.ust.hk
liu.1@nd.edu
T2H02
A2012
2206
Self Adaptive Neural Networks for Blind Separation of Sources
A. Cichocki, S. Amari, M. Adachi and W. Kasprzak
ABS Lab, Saitama, JAPAN
cia@kamo.riken.go.jp
kas@zoo.riken.go.jp
liu.1@nd.edu
T2H03
A2013
2207
Blind identificationof medium with multi-layer structure
Hui Luo and Ruey-Wen Liu
liu.1@nd.edu
T2H04
A3502
1078_inouye
Blind Equalization of Digital Communication Channels Using
Fractionally Spaced Samples
Y. Inouye
Osaka University, Osaka, JAPAN
inouye@sys.es.osaka-u.ac.jp
Tuesday, 10:30 a.m. -- 12:00 p.m., Room N, Poster Sessions
T2N00
Session Title: Analog Signal Processing -- Analog Application Approach
Chair: E. I. El-Masry
Technical University of Nova Scotia, Halifax, NS, CANADA
elmasry@tuns.ca
T2N01
A1411
0022_britton
Low Noise, Low-Power Dissipation Analog LSI Electronics
for Heavy-Ion Detectors
C. Britton, W. Bryan, M. Emery, N. Ericson, M. Musrock,
M. Simpson, J. Walker, A. Wintenberg, F. Plasil, G. Young,
M. Allen, L. Clonts, E. Kennedy, R. Smith J. Boissevain,
B. Jacak, J. Kapustinsky, J. Simon-Gillo, J. Sullivan,
H. vanHecke and N. Xu
Oak Ridge National Laboratory, Oak Ridge, TN
University of Tennessee, Knoxville, TN
Los Alamos National Laboratory, Los Alamos, NM
britton@icsun1.ic.ornl.gov
T2N02
A1412
0862_wuyu2
A New CMOS Readout Circuit Design for the IR FPA with
Adaptive Gain Control and Current-Mode Background Suppression
C.-C. Hsieh, C.-Y. Wu, F.-W. Jih, T.-P. Sin and H. Chang
National Chiao-Tung University, Hsin-Chu, TAIWAN, ROC
Chung Shang Inst. of Science and Technology, Lung-Tam, TAIWAN, ROC
p7911581@alab.ee.nctu.edu.tw
T2N03
A1413
1079_kar
Design and Noise Analysis of an Automotive Accelerometer
E. Joseph, B.K.Kar, R. Rohrkemper and M.Ger
Motorola, ADT, Tempe
Motorola, ADT, Tempe, AZ
Motorola, SPD, Phoenix
Motorola, ACT, Mesa, AZ
kar@act.sps.mot.com
T2N04
A1414
0169_bruun
Noise Properties of CMOS Current Conveyors
E. Bruun
Technical University of Denmark, Lyngby, DENMARK
bruun@ei.dtu.dk
T2N05
A1415
0371_aboualla
CMOS Front End Tuned RF Amplifier
E. Abou-Allam, E.I. El-Masry and T. Manku
University of Southern California, Los Angeles, CA
Technical University of Nova Scotia, Halifax, NS, CANADA
aboualla@bronco.vlsi.tuns.ca
T2N06
A1416
0634_chwei2
A Digital Timing Recovery Scheme for TDMA Digital Mobile Radio
D.-Z. Liu and C.-H. Wei
National Chiao Tung University, Hsin Chu, TAIWAN, ROC
chwei@cc.nctu.edu.tw
T2N06a
Session Title: Digital Signal Processing -- Filtering and Filter Design I
Chair: L. Karam
Arizona State University, Tempe, AZ
karam@asu.edu
T2N07
A2411
1014_artur2
Performance of Complex Chebyshev Approximation in
Delay-Root-Nyquist Filter Design
A. Yardim, L.J. Karam, J.H. McClellan and G.D. Cain
University of Westminster, London, UK
Arizona State University, Tempe, AZ
Georgia Institute of Technology, Atlanta, GA
yardim@cmsa.westminster.ac.uk
T2N08
A2412
0104_pei1
Two Novel Methods for Complex Allpass Filters Design
Using Remez Exchange Algorithm
S. C. Pei and C. C. Tseng
National Taiwan University, Taipei, TAIWAN, ROC
pei@cc.ee.ntu.edu.tw
T2N09
A2413
0228_hanna3
Weighted Least Squares Design of Two-dimensional Zero-Phase
FIR Filters in the Continuous Frequency Domain
M.T. Hanna
University of Bahrain, Isa Town, BAHRAIN
eh049@cc.uob.bh
T2N10
A2414
0152_yr
The Design of Cascaded FIR Filters
Y.C. Lim, R. Yang and B.Liu
National University of Singapore, SINGAPORE
Princeton University, NJ
yr@vlsi.ee.nus.sg
T2N11
A2415
1102_masahide
Convergence Behavior of Evolutionary Digital Filters
on a Multiple-Peak Surface
M. Abe, M. Kawamata and T. Higuchi
Tohoku University, Sendai, JAPAN
masahide@ecei.tohoku.ac.jp
T2N12
A2416
1277_odegard2
Design of Wavelets with a Large Number of Small
Wavelet Moments
J.E. Odegard and C.S Burrus
Rice University, Houston, TX
odegard@rice.edu
T2N12a
Session Title: Digital Signal Processing -- Discrete-Time Circuits and Systems
Chair: P. Bauer
University of Notre Dame, Notre Dame, IN
pbauer@mars.ee.nd.edu
T2N13
A3411
0120_francis
Input-Output Gains of Linear Periodic Discrete-Time
Systems with Application to Multirate Signal Processing
S. Mirabbasi, B. Francis and T. Chen
University of Toronto, Toronto, ON, CANADA
University of Calgary, Calgary, AB, CANADA
francis@control.utoronto.ca
T2N14
A3412
0433_matsu
Approximation of Group Delay Response using Weighted
Least Square Method
K. Matsuyama, M. Okuda and M. Ikehara
Keio University, Yokohama, JAPAN
matsu@tkhm.elec.keio.ac.jp
T2N15
A3413
0701_awang
A Novel DSP System for Microphone Array Applications
A. Wang, K. Yao, R.E. Hudson, D. Korompis, F. Lorenzelli,
S.F. Soli and S. Gao
University of California, Los Angeles, CA
House Ear Institute, Los Angeles, CA
awang@ee.ucla.edu
T2N16
A3414
0728_jenkins1
Adaptive Fault Tolerance in Two-Dimensional Systems
C.D. Schmitz and W.K. Jenkins
University of Illinois, Urbana, IL
jenkins@uicsl.csl.uiuc.edu
T2N17
A3415
0789_hreddy
Efficient Polynomial Transformation Algorithms for Multidimensional Systems
H.C. Reddy, I.-H. Khoo, G.S. Moschytz and A.R. Stubberud
California State University, Long Beach, CA
ETH, Zurich, SWITZERLAND
University of California, Irvine, CA
hreddy@engr.csulb.edu
T2N18
A3416
1095_mahes_kprema
Two-Dimensional Delta-Operator Formulated Discrete-Time
Systems: Analysis and Synthesis of Minimum Roundoff noise Realizations
M.M. Ekanayake and K. Premaratne
University of Miami, Coral Gables, FL
kprema@umiami.ir.miami.edu
T2N19
A4411
0641_ofeely
Bandpass Sigma-Delta Modulation - An Analysis from the
Perspective of Nonlinear Dynamics
O. Feely and D. Fitzgerald
University College, Dublin, IRELAND
OFEELY@CCVAX.UCD.IE
T2N20
A4412
0838_ushidaa
Analysis of Nonlinear Traveling Waves by Frequency-Domain
Perturbation Method
A. Ushida, Y. Tanji and Y. Nishio
Tokushima University, JAPAN
ushida@ee.tokushima-u.ac.jp
T2N21
A4413
0921_furukawa
A Consideration on the Modified Block LMS-Newton Algorithm
and Its Performance
M. Kimoto and T. Furukawa
Fukuoka Institute of Technology, JAPAN
T2N22
A4414
1244_sveinsso
General Stable Factor Perturbations Controllers
J.R. Sveinsson and F.W. Fairman
University of Iceland, Reykjavik, ICELAND
Queen's University, Ontario, CANADA
sveinsso@verk.hi.is
T2N23
A4415
0428_tonydavies
Computing Vasins of Attraction of Limit-Cycles in
Non-Linear Discrete-Time Systems
A.C. Davies and G.P. Petkov
University of London, Strand, London, UK
tonydavies@bay.cc.kcl.ac.uk
T2N24
A4416
0867_pileggi
Analytic Termination Metrics for Pin-to-Pin Lossy
Transmission Lines with Nonlinear Drivers
R. Gupta, J. Willis and L. Pileggi
University of Texas at Austin, TX
pileggi@ece.cmu.edu
T2N25
A5412
0310_vuori
Implementation of a Digital Phase-Locked Loop Using CORDIC Algorithm
J. Vuori
Helsinki University of Technology, Espoo, FINLAND
Jarkko.Vuori@hut.fi
T2N26
A5413
0871_cabrerasd2
A VLSI Array Processor with Embedded Scalability for
Hierarchical Image Compression
M.A. Suriano, V.M. Villalva, J. Vega-Pineda, S.D. Cabrera and Y.-C. Chang
University of Texas at El Paso, TX
cabrera@ece.utep.edu
T2N27
A5414
0920_mitsuru
Design of Parallel Signal Processing System for Real-time
SHD Image Processing
M. Nomure, T. Sawabe, T. Fujii and S. Ono
NTT Optical Systems Laboratories, Yokosuka-Shi, Kanahawa-Ken, JAPAN
mitsuru@exa.onlab.ntt.jp
T2N28
A5415
1242_hummels2
Identification of Error Mechanisms in a Folding and Interpolating ADC
D.M. Hummels, I.N. Papantonopoulos and F.H. Irons
University of Maine, Orono, ME
hummels@eece.maine.edu
T2N29
A5416
3202
Integration of Image Sensor and Image Compression
K. Aizawa, H. Hamamoto, Y. Egi, M. Hatori and J. Yamazaki
University of Tokyo, JAPAN and NHK Sci. and Tech. Res. Labs
aizawa@ee.t.u-tokyo.ac.jp
T2N30
A6411
0586_shwang
Design of Wave-Pipelined 900MHz 16b Ripple-Carry Adder Using Modified NPCPL
H. Choi and S.H. Hwang
Korea Advanced Institute of Science and Technology, Taejon, KOREA
shwang@ee.kaist.ac.kr
hchoi@dalnara.kaist.ac.kr
T2N31
A6412
0901_ivan
Wave Pipelines Via Look-up Tables
E.I. Boemo, S. Lopez-Buedo and J.M. Meneses
Polytechnical University of Madrid, SPAIN
ivan@die.upm.es
buedo@ibm.net
T2N32
A6415
0408_pcheung
Quasi-Delay Insensitive Bus for Fully Asynchronous Systems
P. A. Molina and P. Y. K. Cheung
Imperial College of Science, Technology and Medicine, London, UK
p.cheung@ic.ac.uk
T2N32a
Session Title: Neural Systems and Applications -- Neuromorphic Interchip Communication
Chair: Gert Cauwenberghs
Johns Hopkins University, Baltimore, MD
gert@jhunix.hcf.jhu.edu
T2N33
A7411
3702_andreas
Retinomorphic Systems II: Communication
Kwabena Boahen
California Institute of Technology, Pasadena, CA
buster@pcmp.caltech.edu
T2N34
A7412
1322_zaven
Asynchronous Sampling of 2D arrays Using WTA circuits
Z. Kalayjian, J. Waskiewicz, D. Yochelson and A. Andreou
Johns Hopkins University, Baltimore, MD
zaven@olympus.ece.jhu.edu
T2N35
A7413
1506_bassen
An Analog Approach to Neuromorphic Communication
J. Marienborg, T. Lande, A. Abusland and M. Hovin
Univ. of Oslo, Norway
bassen@ifi.uio.no
T2N36
A7414
1507_aanena
A VLSI Communication Architecture for Stochastically
Pulse-Encoded Analog Signals
Abusland, Hovin and Lande
Univ. of Oslo, Norway
aanena@ifi.uio.no
T2N37
A7415
0413_miller
Simple Pulse Asynchronous State Machines
J. Miller and W. Yang
Harvard University, Cambridge, MA
woody@eecs.harvard.edu
T2N38
A7416
0524_ota
CMOS Implementation of a Pulse-Coded Neural Network
with a Current Controlled Oscillator
Y. Ota and B. Wilamowski
University of Wyoming, Laramie, WY
ota@uwyo.edu
T2N39
A8411
0356_ploeger
Codesign of Hardware, Software, and Algorithms -- A Case Study
J. Wilberg, P. Ploeger, R. Camposano and M. Langevin
GMD-SET,Sankt Augustin, GERMANY
Synopsys Inc., Mountain View, CA
ploeger@gmd.de
T2N40
A8412
0509_fang
Joint Scheduling and Allocation for Low Power
Y. Fang and A. Albicki
University of Rochester, Rochester, NY
lulik@ee.rochester.edu
T2N41
A8413
1020_aboulham
Register Allocation Using Circular FIFOs
I. E. Bennour and E. M. Aboulhamid
Montreal University, Montreal, PQ, CANADA
aboulham@iro.umontreal.ca
T2N42
A8414
1032_chien
A VHDL-based Functional Compiler for Optimum Architecture
Generation of FIR filters
V. Verma and C. Chien
University of California, Los Angeles, CA
chien@janet.ucla.edu
T2N43
A8415
1036_parhi
A Unified Framework for Characterizing Retiming and
Scheduling Solutions
T.C. Denk and K.K. Parhi
University of Minnesota, Minneapolis, MN
parhi@ee.umn.edu
T2N44
A8416
1152_vasily
A Placement-Driven Methodology for High-Level Synthesis
of Sub-micron ASIC's
V. G. Moshnyaga and K. Tamaru
Kyoto University, Kyoto, Japan
vasily@kuee.kyoto-u.ac.jp
T2N45
1556
Static Redundancy Techniques for CMOS Gates
G. Buonanno, C. Bolchini, D. Sciuto and R. Stefanelli
Politecnico di Milano Milano, ITALY
buonanno@elet.polimi.it
T2N46
1561
A Chip-Level Electrothermal Simulator for Temperature
Profile Estimation of CMOS VLSI Chips
Y. K. Cheng, C. C. Teng, A. Dharchoudhury, E. Rosenbaum and S. M. Kang
University of Illinois at Urbana-Champaign, Urbana, IL
yikan@uivlsi.csl.uiuc.edu
T2N47
1557
Improved Variable Ordering of BDDs with Novel Genetic Algorithm
P.Y.K. Cheung
University of LONDON
p.cheung@ic.ac.uk
T2N48
A8016
1905
A New Reliable Approximation Method for Expanded Symbolic
Network Functions
Piet Wambacq, Georges Gielen and Willy Sansen
Katholieke Universiteit Leuven, Heverlee, BELGIUM
Piet.Wambacq@esat.kuleuven.ac.be
huelsman@ece.arizona.edu
marwan@iastate.edu
Tuesday, 1:30 p.m. - 3:00 p.m., Room A
T3A00
Session Title: Analog Signal Processing -- Analog Circuits and Signal Processing
Chair: Terry Sculley
Cypress Semiconductor Corporation, Austin, TX
sculley@crystal.cirrus.com
T3A01
A1501
0065_huangy1
Novel high-frequency track-and-hold stages with offset and gain compensation
Y. Huang, P.F. Ferguson and G.C. Temes
Oregon State University, Corvallis, OR
Analog Devices Inc., Wilmington, MA
temes@ece.orst.edu
T3A02
A1502
0066_huangy2
Reduced Nonlinear Distortion in Circuits with Correlated Double Sampling
Y. Huang, P.F. Ferguson and G.C. Temes
Oregon State University, Corvallis, OR
Analog Devices Inc., Wilmington, MA
temes@ece.orst.edu
T3A03
A1503
1362_simona
A CMOS Sample and Hold for High-Speed ADCs
S. Brigati, F. Maloberti and G. Torelli
University of Pavia, Pavia, ITALY
simona@ipvsp4.unipv.it
T3A04
A1714
Tuesday, 1:30 p.m. - 3:00 p.m., Room A
0028_chiang
A CMOS Fully-Balanced Continuous-Time IFLF Filter
Design for Read/Write Channels
D. Chiang and R. Schaumann
Portland State University, OR
chiang@ee.pdx.edu
Tuesday, 1:30 p.m. - 3:00 p.m., Room B
T3B00
Session Title: Neural Systems and Applications -- Fuzzy Neural Networks
Chair: Fathi Salam
Michigan State University, East Lansing, MI
salam@ee.msu.edu
T3B01
A7501
1178_jsilva
A Very Fast CMOS Artificial Cellular Neural Network
F. Lobato-Lopez, J. Silva-Martinez and E. Sanchez-Sinencio
Instituto Nacional de Astrofisica Optica y Electronica, Puebla, Pue, MEXICO
Texas A & M University, College Station, TX
jsilva@tonali.inaoep.mx
T3B02
A7502
1091_lumi
CMOS Fuzzy Controllers Implemented as Mixed-Signal ICs
I. Baturone, S. Sanchez-Solano, A. Barriga and J. Huertas
Centro Nacional de Microelectronica, Sevilla, SPAIN
lumi@cnm.us.es
T3B03
A7503
0613_neuron
The CMOS Design of Robust Neural Chip with the On-chip
Learning Capability
I-C. Jou, R.-Y. Liu, C.-Y. Wu, and F.-J. Shyh Jye
Telecommunication Laboratories, TAIWAN, ROC
National Chiao Tung University, TAIWAN, ROC
neuron@twnmoctl.bitnet
T3B04
A7504
1156_vidal
CMOS Design of Adaptive Fuzzy ASICs Using Mixed-Signal Circuits
F. Vidal-Verdu, R. Navas and A. Rodriguez-Vazquez
Universidad de Malaga, Malaga, SPAIN
Centro Entro Nacional De Microelectronica,
Universidad De Sevilla, Sevilla, SPAIN
angel@cnm.us.es
Tuesday, 1:30 p.m. - 3:00 p.m., Room C
T3C00
Session Title: Computer-Aided Design -- Logic/High-Level Synthesis
Chair: T. W. Her
Mentor Graphics, San Jose, CA
ross_her@mentorg.com
T3C01
A8501
1127_shiple
Analysis of Combinational Cycles in Sequential Circuits
T. Shiple, V. Singhal, R. Brayton and A. Sangiovanni-Vincentelli
University of California, Berkeley, CA
shiple@eecs.berkeley.edu
T3C02
A8502
1050_fujita
BDD Minimization by Truth Table Permutations
M. Fujita, Y. Kukimoto and R. K. Brayton
Fujitsu Laboratories of America, CA
University of California, Berkeley, CA
fujita@fla.fujitsu.com
T3C03
A8503
1214_papachristou_1
A Scan Path Selection Method for RTL and Mixed Level Circuits
S. Chiu, C. Papachristou and C. Fu
Case Western Reserve University, Cleveland, OH
cap@alpha.cwru.edu
T3C04
A8504
1088_lfc
A Framework for Algebraic Transformations on Iterative Algorithms
J.-F. Shi and L.-F. Chao
Iowa State University, Ames, IA
lfc@iastate.edu
Tuesday, 1:30 p.m. - 3:00 p.m., Room D
T3D00
Session Title: Digital Signal Processing -- Filtering And Filter Design II
Chair: V. DeBrunner
University of Oklahoma, Norman, OK
vdebrunn@uoknor.edu
T3D01
A2501
0097_nikos
Fast Digital Locally Monotonic Regression
N.D. Sidiropoulos
University of Maryland, College Park, MD
nikos@glue.umd.edu
T3D02
A2502
0396_yohlee
Design of Cascade-Form IIR Filters with Powers-of-Two
Coefficients Using Mixed Integer Linear Programming
H. J. Oh, W. J. Oh and Y. H. Lee
Korea Advanced Institute of Science and Technology, Taejon, KOREA
yohlee@eekaist.kaist.ac.kr
T3D03
A2503
0639_wslu
Design of Two-Dimensional FIR Filters Using Norm-Preserving Dialations
W.-S. Lu
University of Victoria, BC, CANADA
wslu@ece.uvic.ca
T3D04
A2504
1386_yanghk
High Speed Polyphase CIC Decimation Filter
H.-K. Yang and W.M. Snelgrove
Carleton University, Ottawa, ON, CANADA
yanghk@doe.carleton.ca
Tuesday, 1:30 p.m. - 3:00 p.m., Room E
T3E00
Session Title: Analog Signal Processing -- Amplifiers
Chair: Sherif H. K. Embabi
Texas A&M University, College Station, TX
embabi@eesun1.tamu.edu
T3E01
A5501
0282_ehsan
A BiCMOS Wideband Operational Amplifier with 900 MHz
Gain-Bandwidth and 90 dB DC Gain
M. Ehsanian and B. Kaminska
Ecole Polytechnique of University of Montreal, Montreal, CANADA
ehsan@grm94.polymtl.ca
T3E02
A5502
0329_embabi
The Limitation of CMRR In Low Voltage Oparational Amplifier
with N-P Input Pairs
F. You, S. Embabi and E. Sanchez-Sinencio
Texas A&M University, College Station, TX
Embabi@eesun1.tamu.edu
T3E03
A5503
0346_holzmann
A Low-Offset Low-Voltage CMOS Op Amp with Rail-to-Rail Input
and Output Ranges
P.J. Holzmann, R.J. Wiegerink, S.L.J. Gierkink, R.F. Wassenaar
MESA Research Institute, University of Twente, Enschede, NETHERLANDS
R.F.Wassenaar@el.utwente.nl
T3E04
A5504
1349_hakki
A Temperature Compensated 100 MHz to 1 GHz Variable Gain Amplifier
in a 8 GHz 1.2 um BiCMOS Process
J. Hakkinen, T. Rahkonen and J. Kostamovaara
University of Oulu, Oulu, FINLAND
hakki@ee.oulu.fi
Tuesday, 1:30 p.m. - 3:00 p.m., Room F
T3F00
Session Title: Nonlinear Circuits & Systems -- Synchronization and
Control of Chaos I
Chairs: Maciej Ogorzalek and Guanrong Chen
University of Mining and Metalurgy, Krakow, Poland
University of Houston, Houston, TX
maciej@fractal.zet.agh.edu.pl
gchen@uh.edu
T3F01
A4501
2803
Analysis of an encoder-decoder-system based on digital filter
structures with two complement overflow characteristics
Kristina Kelber, Torsten Kilias and Marco Gotz
Technical Universitat Dresden, Dresden, GERMANY
abel@iee.et.tu-dresden.de
T3F02
A4502
2804
Digital communication using controlled chaos
Scott Hayes and Celso Grebogi
Army Research Lab
University of Maryland, College Park, MD
kelber@iee.et.tu-dresden.de
T3F03
A4503
2806
Modeling bological control using pulse-coupled circuits
Thomas L Carroll
U. S. Naval Research Lab, Washington, DC
maciej@fractal.zet.agh.edu.pl
gchen@uh.edu
T3F04
A4504
2808
IC design for spread spectrum communication exploiting chaos
M. Delgado-restituto and A. Rodriguez-Vazguez
Universidad de Sevilla, Sevilla, SPAIN
mandel@cnm.us.es
Tuesday, 1:30 p.m. - 3:00 p.m., Room G
T3G00
Session Title: VLSI Systems and Applications -- Low Power Circuits
Chair: David Allstot
Oregon State University
T3G01
A6501
0393_hyhuang
Unbalanced Current Latch Sense Amplifier for Low-Power
High-Speed PLD's
H.Y. Huang and Y.H. Chu
Industrial Technology Research Institute, Chutung, Hsinchu, TAIWAN, ROC
HYHUANG@U1TH1.CCL.ITRI.ORG.TW
T3G02
A6502
0407_bcarlson
Dynamic Circuits for CMOS and BiCMOS Low Power VLSI Design
Z.Zhu and B.S. Carlson
State University of New York at Stony Brook, NY
bcarlson@sbee.sunysb.edu
T3G03
A6503
1038_eesrv
TTL-CMOS Input Buffers with No Static Power Dissipation
S. R. Vemuru
City College of the City University of New York, NY
eesrv@ees1s0.engr.ccny.cuny.edu
T3G04
A6504
1180_kkotani
DC-Current-Free Low-Power A/D Converter Circuitry Using
Dynamic Latch Comparators with Divided-Capacitance Voltage Reference
K. Kotani, T. Shibata and T. Ohmi
Tohoku University, Sendai, JAPAN
kotani@sse.ecei.tohoku.ac.jp
Tuesday, 1:30 p.m. - 3:00 p.m., Room H
T3H00
Session Title: Digital Signal Processing -- Echo Cancellation
Chair: M. Bellanger
CNAM, Paris, FRANCE
bellang@cnam.cnam.fr
T3H01
A3501
0367_moritz
Acoustic Echo Cancelation using a Pseudo-Linear Regression and
QR-Decomposition
M. Harteneck and R. W. Stewart
University of Strathclyde, Glasgow, UK
moritz@spd.eee.strath.ac.uk
T3H02
A3403
1470_ashaw2
A General Look-Ahead Algorithm for Pipelining IIR Filters
A.K. Shaw and M. Imtiaz
Wright State University, Dayton, OH
ashaw@valhalla.wright.edu
T3H03
A3503
1084_klaberte
Maximum DFE Recovery Times for First-Order Channels
K. Laberteaux, J. Kenney, and C. Rohrs
Tellabs Research Center, Mishawaka, IN
klaberte@trc.tellabs.com
T3H04
A3504
1138_tahernez
Subband Based Hands-free phone with Integrated Engine Noise
and Acoustic Echo Cancellation
M. Tahernezhadi
Northern Illinois University, DeKalb, IL
tahernez@ceet.niu.edu
Tuesday, 1:30 p.m. -- 3:00 p.m., Room N, Poster Sessions
T3N00
Session Title: Analog Signal Processing -- Switched-Current Circuits
Chair: John Hughes
Philips Research Labs, Redhill, Sussex, UK
hughesjb@prl.philips.co.uk
T3N01
A1511
0067_hughesjb
Enhanced S2I Switched-Current Cells
J.B.Hughes and K.W.Moulding
Philips Research Labs, Redhill, Sussex, UK
hughesjb@prl.philips.co.uk
T3N02
A1512
0068_huxi
A Switched-Current Sample-and-Hold Circuit
X. Hu and K. Martin
University of Toronto, Toronto, ON, CANADA
martin@eecg.toronto.edu
T3N03
A1513
1057_helfenst
Design Techniques for HDTV Switched-Current Decimators
M. Helfenstein, J.E. Franca and G.S. Moschytz
Swiss Institute of Technology, Zurich, SWITZERLAND
Instituto Superior Technico, Lisboa, PORTUGAL
helfenst@isi.ee.ethz.ch
T3N04
A1514
1068_jopa
A Digitally Calibrated Current-Mode Two-Step Flash A/D Converter
J. Oliveira, J. Vital and J.E. Fraca
Instituto Superior Tecnico, Lisbon, Codex, PORTUGAL
joao@ecsm4.ist.utl.pt
T3N05
A1515
1413_elmasry_toole
A Novel Highly Linear 1 GHz Switched Current Sub-sampling Mixer
W. Toole, E. El-Masry and T. Manku
Technical University of Nova Scotia, Halifax, NS, CANADA
elmasry@tuns.ca
T3N06
A1516
0157_wey5
A 5mW, 12-b, 50ns/b Switched-current Cyclic A/D Converter
R. Huang and C.-L. Wey
Michigan State University, East Lansing, MI
wey@ee.msu.edu
T3N06a
Session Title: Digital Signal Processing -- DSP Implementation I
Chair: K. Parhi
University of Minnesota, Minneapolis, MN
parhi@ee.umn.edu
T3N07
A2511
0178_agarwal
Recursive Implementation of Statistically-Optimal Null Filters
R. Agarwal, E.I. Plotkin, and M.N.S. Swamy
Concordia University, Montreal, QC, CANADA
eugene@ece.concordia.ca
T3N08
A2512
0351_sugino
Improved Code Optimization Method Utilizing Memory Addressing
Operation and its Application to DSP Compiler
N. Sugino, H. Miyazaki, S. Iimuro and A. Nishihara
Tokyo Institute of Technology, Meguro-ku, Tokyo, JAPAN
sugino@ss.titech.ac.jp
T3N09
A2513
0739_bull4
Genetic Algorithm Based DSP Multiprocessor Scheduling
R.W. Amphlett and D.R. Bull
University of Bristol, Bristol, UK
Dave.Bull@bristol.ac.uk
T3N10
A2514
1229_wkreuzer
A Retargetable Optimizing Code Generator for Digital Signal Processors
W. Kreuzer, B. Wess and M. Gotschlich
Technical University Vienna, Vienna, AUSTRIA
wkreuzer@email.tuwien.ac.at
T3N11
A2515
0145_winser
A High Performance Parallel Architecture for the Least Squares Method
H. Ko and W. Alexander
LG Semicon Co., Ltd. KOREA
North Carolina State University, Raleigh, NC
winser@eos.ncsu.edu
T3N12
A2516
1279_jon_mellot
ASAP: A VLSI DSP Vector Processor
J.D. Mellott, M. Lewis, F.J. Taylor and P. Coffield
The Athena Group and the University of Florida, Gainesville, FL
The Athena Group, Gainesville, FL
University of Florida, Gainesville, FL
USAF Wright Lab, Eglin AFB, FL
jon@alpha.ee.ufl.edu
T3N12a
Session Title: Digital Signal Processing -- A/D and D/A Conversion I
Chair: H. Tenhunen
The Royal Institute of Technology, Kista, Sweden
hannu@ele.kth.se
T3N13
A3511
0129_toyo
High-Speed Hardware Algorithms for Chinese Remainder Theorem
H. Toyoshima, K. Satoh and K. Ariyama
Kanagawa University, Kanagawa, JAPAN
toyo@tysm0.b6.kanagawa-u.ac.jp
T3N14
A3512
0340_rfellman
CMOS VLSI Implementation of Gigabyte/ Second Computer Network Links
M. Bendak, R. Fellman and P. Chau
University of California, San Diego, CA
rfellman@ucsd.edu
T3N15
A3513
0363_es
VLSI Implementation of a Sigma-Delta Bitstream FIR Filter
S.Summerfield, M.Anderson, S.Kershaw and M.Sandler
University of Warwick, Coventry, UK
King's College, University of London, UK
es285@eng.warwick.ac.uk
T3N16
A3514
1010_ant
Performance Enhancement of Sigma-Delta Modulator D-A Converters
Using Non-linear Techniques
A.J. Magrath and M.B. Sandler
King's College London, UK
ant@orion.eee.kcl.ac.uk
T3N17
A3515
1140_terri
Digital Comb Filter Implementation for the Pi Delta Sigma A/D Converter
S. Sculley and T. Fiez
Cypress Semiconductor Corporation, Austin, TX
Washington State University, Pullman, WA
terri@eecs.wsu.edu
T3N18
A3516
1147_ts
An Efficient Approach for Conversion Between Arbitrary Sampling Frequencies
T. Saramaki and T. Ritoniemi
VLSI Solution Oy, Tampere, FINLAND
ts@cs.tut.fi
T3N19
A4511
1012_moreau
A Lie algebraic approach to dynamical system prediction
Y. Moreau and J. Vandewalle
Katholieke Universiteit, Leuven, BELGIUM
moreau@esat.kuleuven.ac.be
T3N20
A4512
1478_koichi
Realization Theory of Continuous-Time Pseudo Linear Systems
Y. Hasegawa Gifu
University, Gifu, JAPAN
koichi@cc.gifu-u.ac.jp
T3N21
A4513
0113_reiszig
Computing the Generic Index of the Circuit Equations of
Linear Active Networks
G. Reiszig and U. Feldmann
Technische Universitaet Dresden, GERMANY
reiszig@iee.et.tu-dresden.de
T3N22
A4514
0139_wey2
A Test Paradigm for Analog and Mixed-Signal Circuits and Systems
C.-P. Wang, A.A. Hatzopoulos and C.-L. Wey
Michigan State University, East Lansing, MI
Aristotle University of Thessaloniki, Thessaloniki, GREECE
wey@ee.msu.edu
T3N23
A4515
1217_deFigueiredo_chen
A Wavelet-Based Fock Space: A New Multi-Scale Space
for Nonlinear Dynamical Systems
R.J.P. de Figueiredo and G. Chen
University of California, Irvine, CA
University of Houston, Houston, TX
gchen@uh.edu
T3N24
A4516
0843_nishio
Analysis of Chua's Circuit with Transmission Line
J. Kawata, Y. Nishio and A. Ushida
Tokushima Bunri University, Okawa, Kagawa, JAPAN
nishio@ee.tokushima-u.ac.jp
T3N24a
Session Title: Analog Signal Processing -- Analog Application Approaches II
Chair: Bill Kuhn
Virginia Polytechnic Institute and State University, Blacksburg, VA
T3N25
A5511
1203_mrossi
Two Fast Convergent Algorithms for the Design of
Equiripple IIR an FIR Filters in the Log Magnitude Sense
M. Rossi, J.-Y. Zhang and W. Steenaart
University of Ottawa, Ottawa, ON, CANADA
Bell Northern Research, Ottawa, ON, CANADA
mrossi@bnr.ca
T3N26
A5512
1225_bryn
Power Design: A Module Generator for General-Purpose Amplifiers
S. Rezania and K.W. Martin
University of Toronto, Toronto, ON, CANADA
martin@chaos.eecg.toronto.edu
T3N27
A5513
0706_eedenny
Gain Stage Design Based on Narrow-Width Methodology in SOI Technology
D. Cheung, J. Lau and P. Chan
Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, HONG KONG
eedenny@ee.ust.hk
T3N28
A5514
0016_bergou
Designs for a Wideband Logarithmic Amplifier
F. Bergouignan, L. Jomain, F. Marionnet, N. Abouchi, R. Grisel
ICPI CPE LYON, Lyon Cedex, FRANCE
abouchi@cpe.ipl.fr
T3N29
A5515
0089_mensink
On the Reduction of the Third Order Distortion in a CMOS Triode Transconductor
C.H.J. Mensink, E.A.M. Klumperink and B. Nauta
University of Twente, Enschede, NETHERLANDS
Philips Research Lab., Eindhoven, NETHERLANDS
c.h.j.mensink@el.utwente.nl
T3N30
A6511
1013_apurusho
A Closed-Loop Micromotor Control System
A. Purushotham, S. L. Garverick, C. Edwards and M. Nagy
Case Western Reserve University, Cleveland, OH
apurusho@mipos2.intel.com
T3N31
A6512
1023_bjarthur
A Silicon Model of the Auditory Neural Perception of Frequency Modulation
B.J. Arthur and C.A. Mead
California Institute of Technology, Pasadena, CA
bjarthur@pcmp.caltech.edu
T3N32
A6513
1194_konda
Neuron-MOS Correlator based on Manhattan Distance Computation
for Event Recognition Hardware
M. Konda, T. Shibata and T. Ohmi
Tohoku University, Sendai, JAPAN
konda@sse.ecei.tohoku.ac.jp
T3N33
A6514
1292_rhodson
A Content Addressable Memory with Independent Byte and
Partial Match Capabliity
R.F. Hodson, D.C. Doughty, D. Allgood and W.C. Wilson
Christopher Newport University, VA
NASA Langley, VA
rhodson@pcs.cnu.edu
T3N34
A6515
1338_danny_cycu
Design of Pyroelectric IR Readout Circuit Based on LiTaO3 Detectors
W.-Y. Chung, H.-M. Hong, T.-P. Sun, C.-Y. Leung, H.-C. Lai,
Y.-L. Kao and Y.-L. Chin
Chung-Yuan University, Chung-Li, TAIWAN, ROC
National Central University, Chung-Li, TAIWAN, ROC
Chung Shan Inst. of Science and Technology, Long Tan, Taoyuan, TAIWAN, ROC
danny@vlsi.cycu.edu.tw
T3N35
A6516
1368_yuichiro_shibata
Write/Verify-Free Analog Non-Volatile Memory Technology
using a Neuron-MOS comparators
Y. Yamashita, T. Shibata and T. Ohmi
Tohoku University, Sendai, JAPAN
shibata@sse.ecei.tohoku.ac.jp
T3N35a
Session Title: Neural Systems and Applications -- Applications I
Chair: Gregory L. Creech
Wright Laboratory, Dayton, OH
creech@el.wpafb.af.mil
T3N36
A7511
0216_ywkim2
Blind Separation of Sources Using Decorrelation Process
K.-S. Eom and D.-J. Park
Korea Advanced Institute of Science and Technology, Taejon, KOREA
djpark@eekaist.kaist.ac.kr
T3N37
A7512
0389_jinno
Fast Analysis Algorithm for Hysteresis Neural Networks
and its Application for Classification of Chaos
K. Jin'no, T. Nakamura and T. Saito
Hosei University, Koganei-shi, Tokyo, JAPAN
jinno@toshi.ee.hosei.ac.jp
T3N38
A7513
0179_tavsanav
Absolute Stability of Nonsymmetric Neural Networks
S. Arik and V. Tavsanoglu
South Bank University, London, UK
tavsanav@vax.sbu.ac.uk
T3N39
A7514
0134_victor1
Sensitivity and Learning of Two Digital Artificial Neural Network Structures
V. E. DeBrunner, S.-C. Li and S. Lewandowsky
University of Oklahoma, Norman, OK
Max Plank Institute, Berlin, GERMANY
University of Western Australia, Nedlands, W.A. AUSTRALIA
vdebrunn@uoknor.edu
T3N40
A7515
0387_jmzura2
Dynamics of Error Backpropagation Learning with Pruning in the Weight Space
A. Lozowski, D.A. Miller and J.M. Zurada
University of Louisville, Louisville, KY
jmzura02@starbase.spd.louisville.edu
T3N41
A7516
0382_jmzura
Inverse Mapping with Neural Network for Control of Nonlinear Systems
A. Malinowski, T. J. Cholewo, J. M. Zuradaand P. B. Aronhime
University of Louisville, Louisville, KY
jmzura02@starbase.spd.louisville.edu
T3N42
A8511
0001_acmq
Statistical Prediction of Errors in the Location of Poles
and Zeros by Sensitivity Analysis
A. C. Moreirao de Queiroz and L. P. Caloba
Universidade Federal do Rio de Janeiro, BRAZIL
acmq@coe.ufrj.br
T3N43
A8512
0072_jendges
A Relaxation Approach to Simulation Assistance
R. Jendges
German National Research Center for Information Technology,
St. Augustin, GERMANY
jendges@gmd.de
T3N44
A8513
0177_nowacka
Circuit Models for the Hybrid Element Method
P.M. Dewilde and E.B. Nowacka
Delft University of Technology, Delft, NETHERLANDS
nowacka@cas.et.tudelft.nl
T3N45
A8514
0359_jw
Simulation of Circuits with Inconsistent Initial Conditions
J. Wojciechowski, Z. Michalski and J. Vlach
Warsaw University of Technology, Warsaw, POLAND
University of Waterloo, Waterloo, ON, CANADA
jwojc@ipe.pw.edu.pl
T3N46
A8515
0946_jvlach
Accelerated almost periodic steady state of switched networks
L. Zhu, J. Vlach and J. Valsa
University of Waterloo, Waterloo, ON, CANADA
Technical University of Brno, Brno, CZECH REPUBLIC
jvlach@vlsi.uwaterloo.ca
T3N47
A8516
1085_ktlee
Analysis of Cross Talk Effects in VLSI Digital Circuits
K.T. Lee and J.A. Abraham
University of Texas, Austin, TX
ktlee@cerc.utexas.edu
T3N48
1551
Combinationally Irredundant ISCAS-89 Benchmark Circuits
S. Kajihara, K. Kinoshita, I. Pomeranz and S. Reddy
University of Iowa, Iowa City, IA
reddy@hitchcock.eng.uiowa.edu
T3N49
1552
Analog Circuit Placement: A Constraint Driven Methodology
F. Salice
Dipartimento di Electtronica e Informazione, Milano, ITALY
salice@elet.polimi.it
Tuesday, 3:30 p.m. - 5:00 p.m., Room A
T4A00
Session Title: Analog Signal Processing -- Element Mismatch Considerations
Chair: Ken Martin
University of Toronto, Toronto, ON, CANADA
martin@eecg.toronto.edu
T4A01
A1601
1135_steve
The Effects of Mismatch in Complex Bandpass Delta-Sigma Modulators
S.A. Jantzi, K.W. Martin and A.S. Sedra
University of Toronto, Toronto, ON, CANADA
steve@eecg.toronto.edu
T4A02
A1602
1270_olivier
An Analysis of Dynamic Element Matching Techniques in Sigma -Delta Modulation
O. Nys
Swiss Center for Electronics and Microtechnology (CSEM), SWITZERLAND
olivier.nys@morgon.csemne.ch
T4A03
A1603
0165_linha
Multi-Bit DAC with Noise-Shaped Element Mismatch
R. Schreier, H. Lin, J.B. Silva and B. Zhang
Oregon State University, Corvallis, OR
IST Centre for Microsystems, Lisbon, PORTUGAL
schreier@ece.orst.edu
T4A04
A1604
0296_bminch
The Matching of Small Capacitors for Analog VLSI
B. A. Minch, C. Diorio, P. Hasler and C. Mead
California Institute of Technology, Pasadena, CA
bminch@pcmp.caltech.edu
Tuesday, 3:30 p.m. - 5:00 p.m., Room B
T4B00
Session Title: Neural Systems and Applications -- Filtering for Neural Networks
Chair: Bing Sheu
University of Southern California, Los Angeles, CA
sheu@pacific.usc.edu
T4B01
A7601
0651_andreas1
Design of IIR Filters with Arbitrary Amplitude and
Phase Specifications by Feedback Neural Networks
D. Bhattacharya and A. Antoniou
University of Victoria, BC, CANADA
andreas@ece.uvic.ca
T4B02
A7602
0320_jullien
Parallel Median Filtering Using Cellular Neural Networks
S. Emamchaie, G.A. Jullien and W.C. Miller
University of Windsor, ON, CANADA
sadeghi@engn.uwindsor.ca
T4B03
A7603
0149_yeng
Monitoring and Diagnosis of Vibration Signatures in Rotorcraft Machines
G. Yen
University of New Mexico, Albuquerque, NM
yeng@plk.af.mil
T4B04
A7604
0675_mohei
The Robust Prediction Problem for a Class of Uncertain Systems
S.O. Reza Moheimani, A.V. Savkin and I.R. Petersen
University of New South Wales, Canberra, AUSTRALIA
irp@ee.adfa.oz.au
Tuesday, 3:30 p.m. - 5:00 p.m., Room C
T4C00
Session Title: Computer-Aided Design -- System-Level Synthesis
Chair: Liang-Fang Chao
Iowa State University, Ames, IA
lfc@iastate.edu
T4C01
A8601
0308_dasgupta
RELSYN: A tool for synthesis of Reliable Application Specific Multiprocessors
A. Dasgupta and R. Karri
Univ of Massachusetts, Amherst, MA
dasgupta@ecs.umass.edu
T4C02
A8602
0704_rgupta
Software Synthesis for Embedded Systems
R.K. Gupta
University of Illinois, Urbana-Champaign, IL
rgupta@cs.uiuc.edu
T4C03
A8603
0834_shinh2
Parititioning for Minimal Memory in Hardware-Software Codesign
D. Park and H. Shin
Hanyang University, KOREA
shin@hyunp2.hanyang.ac.kr
T4C04
A8604
0181_cchantra
Minimization of Fuzzy Systems based on Fuzzy Inference Graphs
C.Chantrapornchai, S. Tongsima and E.H.M. Sha
University of Notre Dame, Notre Dame, IN
esha@bach.helios.nd.edu
Tuesday, 3:30 p.m. - 5:00 p.m., Room D
T4D00
Session Title: Digital Signal Processing -- DSP Implementation II
Chair: M. Swamy
Concordia University, Montreal, QC, CANADA
swamy@ece.concordia.ca
T4D01
A2601
0314_chd2
Implementing Narrow-Band FIR Filters Using FPGAs
C. Dick and F. Harris
La Trobe University, Melbourne, AUSTRALIA
San Diego State University, San Diego, CA
chd@ee.latrobe.edu.au
T4D02
A2602
0354_mitsuhik
Minimization of Adders in Multiplierless Linear Phase FIR Digital Filters
M. Yagyu, A. Nishihara and N. Fujii
Tokyo Institute of Technology, Meguro-ku, Tokyo, JAPAN
mitsuhik@ss.titech.ac.jp
T4D03
A2603
1016_gbaccarani2
A 3.5 ns, 64 bit Carry-Lookahead Adder
D. Dozza, M. Gaddoni and G. Baccarani
Universita di Bologna, Bologna, ITALY
gbaccarani@deis.unibo.it
T4D04
A2604
0118_russell
A High throughput Adaptive DFE for HiperLan
R. Perry, D. R. Bull and A. Nix
Bristol University, Bristol, UK
Russ.Perry@Bristol.ac.uk
Tuesday, 3:30 p.m. - 5:00 p.m., Room E
T4E00
Session Title: Analog Signal Processing -- Analog Building Blocks I
Chair: Jaime Ramirez-Angulo
New Mexico State University, Las Cruces, NM
jramirez@nmsu.edu
T4E01
A5601
0864_jramirez2
+-0.75V BiCMOS Four Quadrant Analog Multiplier with
Rail-Rail Input Signal-Swing
J. Ramirez-Angulo
New Mexico State University, Las Cruces, NM
jramirez@nmsu.edu
T4E02
A5602
1164_michael
A New Building Block in CMOS Technology
M .C. Layos and I. Haritantis
University of Patras, Patras, GREECE
michael@physics.upatras.gr
T4E03
A5603
1210_hua_lmoldovan
A Buffered, Constant Gain, OPAMP with Rail-to-Rail Common-Mode Range
L. Moldovan and H. Li
Texas Tech University, Lubbock, TX
hua@cs.ttu.edu
T4E04
A5604
0349_nfjg
A CMOS Digitally-Programmable Current Multiplier
N. Paulino and J. E. Franca
Instituto Superior Tecnico, IST Centre for Microsystems,
Integrated Circuits and Systems Group, Lisbon, PORTUGAL
franca@ecsm4.ist.utl.pt
Tuesday, 3:30 p.m. - 5:00 p.m., Room F
T4F00
Session Title: Nonlinear Circuits & Systems -- Synchronization and
Control of Chaos II
Chairs: Maciej Ogorzalek and Guanrong Chen
University of Mining and Metalurgy, Krakow, Poland
University of Houston, Houston, TX
maciej@fractal.zet.agh.edu.pl
gchen@uh.edu
T4F01
A4601
2809
Chaos synchronization: Enhancing synchronism and synchronizing
hyperchaos with a scalar transmitted signal
Mingzhou Ding
Florida Atlantic University, Boca Raton, FL
ding@walt.ccs.fau.edu
T4F02
Information processing in systems with deterministic chaos
Alexander S. Dmitriev
Institute of Radioengineering & Electronics
of the Russian Academy of Sciences
dmit@chaos.msk.su
T4F02 -- withdrawn
A4602
2813
Estimation and Control of chaotic nonlinear dynamical systems
using time series data
Guanrong Chen
gchen@uh.edu
T4F03
A4603
2814
Fuzzy modeling and control of chaotic systems
Hua O. Wang, Kazuo Tanaka
maciej@fractal.zet.agh.edu.pl
T4F04
A4604
2818
Control and anti-control of chaos with applications in biological systems
William L. Ditto
maciej@fractal.zet.agh.edu.pl
Tuesday, 3:30 p.m. - 5:00 p.m., Room G
T4G00
Session Title: VLSI Systems and Applications -- VLSI Interconnections
Chair: Charles Britton
Oak Ridge National Lab, Oak Ridge, TN
T4G01
A6601
0093_mkl2
A Fringing and Coupling Interconnect Line Capacitance Model
for VLSI On-chip Wiring Delay and Crosstalk
M. Lee
Sharp Microelectronics Technology, Inc., Camas, WA
mkl@sharpwa.com
T4G02
A6602
0435_abk
An Analytical Delay Model for RLC Interconnects
A.B. Kahng and S. Muddu
University of California, Los Angeles, CA
abk@cs.ucla.edu
T4G03
A6603
0436_abk2
New Diffusion-Based Analyses of Distributed RC Interconnections
A.B. Kahng and S. Muddu
University of California, Los Angeles, CA
abk@cs.ucla.edu
T4G04
A6604
1416_dehkordi
Performance Comparison of MCM-D and SMT Packaging Technologies
for a DSP Subsystem
P. Dehkordi, T. Powell and D. Bouldin
University of Tennessee, Knoxville, TN
dehkordi@microsys5.engr.utk.edu
Tuesday, 3:30 p.m. - 5:00 p.m., Room H
T4H00
Session Title: Digital Signal Processing -- High Fidelity Data Compression I
Chairs: N. Magotra, G. Mandyam and S. Stearns
University of New Mexico, Albuquerque, NM
magotra@unm.edu
gmandyam@eece.unm.edu
Sandia National Laboratories, Albuquerque, NM
sdstear@sandia.gov
T4H01
A3601
2301
Lossless compression of images employing a linear IIR model
Yousef W. Nijim, Wasfy B. Mikhael and Samuel D. Stearns
University of Central Florida, Orlando, FL
Sandia National Labs, Albuquerque, NM
wbm@engr.ucf.edu
gmandyam@eece.unm.edu
magotra@unm.edu
sdstear@sandia.gov
T4H02
A3602
2306
A comparison of the prediction schemes proposed for a new
standard for lossless coding of continuous-tone still images
Nasir Memon and Xiaolin Wu
Northern Illinois University
University of Western Ontario
gmandyam@eece.unm.edu
magotra@unm.edu
sdstear@sandia.gov
T4H03
A3603
2303
Lossless compression of electroencephalographic EEG data
Mingui Sun, Neeraj Magotra and Giridhar Mandyam
University of New Mexico, Albuquerque, NM
gmandyam@eece.unm.edu
magotra@unm.edu
sdstear@sandia.gov
T4H04
A3604
2304
Speech coding using the discrete energy separation (DESA) in subbands
Robert K. Whitman and Delores M. Etter
University of Colorado, Boulder, CO
gmandyam@eece.unm.edu
magotra@unm.edu
sdstear@sandia.gov
Tuesday, 3:30 p.m. - 5:00 p.m., Room N, Poster Sessions
T4N00
Session Title: Analog Signal Processing -- Filter Theory and Design
Chair: Marcio Schneider
T4N01
A1611
0650_carlos2
Digitally Programmable Switched Current Filters
R.T. Goncalves, S. Noceti Filho, M.C. Schneider and C. Galup-Montoro
LEG, EPFL, Lausanne, SWITZERLAND
LINSE, University F. de Santa Catarina, BRAZIL
carlos@linse.ufsc.br
T4N02
A1612
0622_tsuku
Novel Electronically Tunable Current-Mode Filter without
External Passive Elements
T. Tsukutani, M. Ishida, S. Tsuiki and Y. Fukui
Matsue National College of Technology, Matsue, Shimane, JAPAN
Tottori University, Tottori, JAPAN
tsuku@hp720.matsue-ct.ac.jp
T4N03
A1613
0102_oralkan
Design of All-Pole Low-Pass Ladder Filters using Current-Mode
Damped Integrators
O. Oralkan, A. I. Karsilayan and M. A. Tan
Bilkent University, Ankara, TURKEY
m.tan@ieee.org
T4N04
A1614
0406_kap
Pulse Based Signal Processing: VLSI implementation of a PALMO FILTER
K. Papathanasiou and A. Hamilton
University of Edinburgh, SCOTLAND, UK
kap@ee.ed.ac.uk
T4N05
A1615
0899_entbah
New Dual Output Transconductance Amplifier-Based Biquad Configuration
B. Al-Hashimi
Staffordshire University, Stafford, UK
entbah@staffs.ac.uk
T4N06
A1616
0273_haoues
An Area Efficient Low Noise 100Hz Low-pass filter
Christian Olgaard and D.H. Sassene
Technical University of Denmark, Lyngby, DENMARK
haoues@id.dtu.dk
T4N06a
Session Title: Digital Signal Processing -- Multirate and Filter Banks II
Chair: T. Chen
AT&T Bell Laboratories, Holmdel, NJ
tsuhan@research.att.com
T4N07
A2611
0432_tsutsui
Design of Perfect Reconstruction FIR Filter Banks
Using DFT-Modulation
S. Tsutsui, T. Nagai and M. Ikehara
Keio University, Kanagawa, JAPAN
tsutsui@tkhm.elec.keio.ac.jp
T4N08
A2612
0027_chent
Minimax Design of Hybrid Multirate Filter Banks
H. Shu, T. Chen and B. A. Francis
University of Calgary, Calgary, AB, CANADA
University of Toronto, Toronto, ON, CANADA
chent@enel.ucalgary.ca
T4N09
A2613
0430_nagai
Design of Over Sampled Perfect Reconstruction FIR Filter Banks
T. Nagai and M. Ikehara
Keio University, Kanagawa, JAPAN
nagai@tkhm.elec.keio.ac.jp
T4N10
A2614
0894_yuyue
Compactly Supported Sampling Function for Wavelet Subspaces
Yue Yu and Youan Ke
Beijing Institute of Technology, Beijing, CHINA
youanke@public.bta.net.cn
T4N11
A2615
0205_kkurosaw
Existency of Two-Dimensional FIR PR QMF System
K. Kurosawa
Tokyo Institute of Technology, Meguro-ku, Tokyo, JAPAN
kkurosaw@ss.titech.ac.jp
T4N12
A2616
0637_lu
Low-Delay Cosine-Modulated QMF Bank for MPEG Audio Compression
H. Xu, W.-S. Lu and A. Antoniou
University of Victoria, BC, CANADA
andreas@ece.uvic.ca
T4N12a
Session Title: Digital Signal Processing -- M-D CAS and Signal Processing I
Chair: H. C. Reddy
California State University, Long Beach, CA
hreddy@engr.csulb.edu
T4N13
A3611
3006
2D linear phase frequency sampling filters and 2-D linear
phase frequency sampling filters with fourfold symmetry
Peter A. Stubberud
University of Nevada, Las Vega, NV
hreddy@eng.uci.edu
T4N14
A3612
3007
An iterative formulation for the least squares approximation
of 2-D signals
Albert P. Berg and Wasfy Mikhael
Lockheed-Martin Corp., Orlando, FL
University of Central Florida, Orlando, FL
aberg@dspsparc.engr.ucf.edu
wbm@engr.ucf.edu
T4N15 -- WITHDRAWN
A3613
3008
On potential applications of 3D space-time filters
Len Bruton
University of Calgary, Calgary, CANADA
bruton@enel.ucalgary.ca
T4N16
A3614
3009
Study of various symmetries in the frequency response of
two-dimensional delta operator formulated discrete - time systems
H. C. Reddy and P. K. Rajan
California State University, Long Beach, CA
hreddy@engr.csulb.edu
T4N17
A3615
3010
Delta-operator formulated discrete-time systems
Kamal Premaratne and Peter H. Bauer
University of Miami, Coral Gables, FL
University of Notre Dame, Notre Dame, IN
kprema@umiami.ir.miami.edu
T4N18 -- WITHDRAWN
A3616
3011
Numerical integration of partial differential equations
using wave digital techniques
Alfred Fettweis
University of Notre Dame, Notre Dame, IN
fettweis@cse.nd.edu
hreddy@eng.uci.edu
T4N19
A4611
1366_jia1_cityu_jk
Switched Capacitor Nonlinear Circuits Derived from Chua's Circuit
X. D. Jia and R. M. M. Chen
City University of Hong Kong, HONG KONG
jia@cpeelgx03.cityu.edu.hk
T4N20
A4612
1412_galton_2
Clock Distribution Using Coupled Oscillators
I. Galton, H.T. Jensen, J.J. Rosenberg and D.A. Towne
University of California, Irvine, CA
Harvey Mudd College, Claremont, CA
galton@ece.uci.edu
T4N21
A4613
0054_felderhoff
A New Wave Description for Nonlinear Elements
T. Felderhoff
University of Paderborn, Paderborn, GERMANY
felderhoff@fli.sh.bosch.de
T4N22
A4614
0515_vdrogoreanu
A Class of MOS Non-Linear Negative Resistance Oscillators
V. Drogoreanu and D. Vizireanu
Politechnical University, Bucharest, ROMANIA
valentin@vala.elia.pub.ro
T4N23
A4615
1245_jcpedro
Prediction of PLL Frequency Discriminator Non-Linear Distortion
Using the Volterra Series Approach
N.B. Carvalho, R.C. Madureira and J.C. Pedro
University of Aveiro, Aveiro, PORTUGAL
jcpedro@gm400.det.ua.pt
T4N24
A4616
0018_birru
Noise Shaping With Reduced Clock Frequency
B. Dagnachew
Philips Research Laboratories, Eindhoven, NETHERLANDS
birru@prl.philips.nl
T4N24a
Session Title: Analog Signal Processing -- Analog Circuits
Chair: Mohammad Ismail
Ohio State University, Columbus, OH
ismail@ee.eng.ohio-state.edu
T4N25
A5611
1312_shuchan
Low-Voltage Linear V-I Converter with Rail-to-Rail Input Range
S.-C. Huang
Tatung Institute of Technology, Taipei, TAIWAN, ROC
shuchuan@cad.ee.ttit.edu.tw
T4N26
A5612
0721_larsen1
A Continuous-Time Offset Compensated HIgh Speed BiCMOS Comparator
F. Larsen and M. Ismail
AT&T Bell Laboratories, Allentown, PA
Ohio State University, Columbus, OH
larsen@aloft.att.com
T4N27
A5613
0627_danilo
An Analog Memory for a QCIF format image frame storage
D. Gerna, M. Brattoli, E. Chioffi, G. Colli, M. Pasotti and A. Tomasini
SGS-Thomson Microelectronics - Agrate B. (MI), ITALY
danilo@sgs-thomson.it
T4N28
A5614
1275_henderson
Dynamic Element Matching Techniques with Arbitrary Noise
Shaping Function
R. Henderson
Swiss Center for Electronics and Microtechnology (CSEM), SWITZERLAND
robert.henderson@csemne.ch
T4N29
A5615
1454_drf3
An Adaptive Analog Notch Filter Using Log Filtering
D. Frey and L. Steigerwald
Lehigh University, Bethlehem, PA
drf3@lehigh.edu
T4N30
A5616
0723_larsen3
The First Fully Balanced, Rail-to-rail, 3V, Class-AB Op Amp
F. Larsen
AT&T Bell Laboratories, Allentown, PA
larsen@aloft.att.com
T4N31
A6611
0199_nemouchi
A reference data oriented approach for implementing a
multiresolution block-matching algorithm
Y. Nemouchi, Y. Mathieu and C. Havet
Ecole Nationale Superieure des Telecommunications, Paris, FRANCE
nemouchi@elec.enst.fr
T4N32
A6612
0410_jeemee
New MPEG2 Decoder Architecture Using Frequency Scaling
J.M. Kim and S.I. Chae
Seoul National University, Gwanak-Gu, Seoul, KOREA
chae@belle.snu.ac.kr
T4N33
A6613
0602_hgk
A High-Performance Distributed Arithmetic Processor for
the High-Definition Video Compression
H.G. Kim and Y.M. Kwon
Korea Inst. of Science and Technology, Seoul, KOREA
hgk@willow.kist.re.kr
T4N34
A6614
1278_chaitali
Hardware Implementation of a 2D Motion Estimation System based
on the Hough Transform
H. Li and C. Chakrabarti
Arizona State University, Tempe, AZ
chaitali@asu.edu
T4N35
A6615
1314_sgchen
New Redundant CORDIC Algorithms with Fast Variable Scale Factor Compensations
C.-C. Li and S.-G. Chen
National Chiao Tung University, Hsinchu, TAIWAN, ROC
sgchen@mets.ee.nctu.edu.tw
T4N36
A6616
1236_paliuras
A Novel Algorithm for Accurate Logarithmic Number System Subtraction
V. Paliouras and T. Stouraitis
University of Patras, Patras, GREECE
paliuras@ee.upatras.gr
T4N36a
Session Title: Neural Systems and Applications -- Hardware Implementation III
Chair: Alister Hamilton
University of Edinburgh, Edinburgh, SCOTLAND, UK
T4N37
A7611
0362_vanja
A Generic Building Block for Hopfield Neural Networks with
On-Chip Learning
M. Gschwind, V. Salapura and O. Maischberger
Techische Universitaet Wien, Vienna, AUSTRIA
vanja@vlsivie.tuwien.ac.at
T4N38
A7612
0589_hikawa
Frequency-based Multilayer Neural Network with On-chip Learning
H. Hikawa
Oita University, Oita, JAPAN
hikawa@csis.oita-u.ac.jp
T4N39
A7613
0309_woody
Neuromorphic CMOS Circuitry for Active Bidirectional Delay Lines
W. Yang
Harvard University, Cambridge, MA
woody@eecs.harvard.edu
T4N40
A7614
0965_bmendil
Hardware Oriented Fuzzy Neural Network
B. Mendil and K. Benmahammed
University of Setif, ALGERIA
T4N41
A7615
1006_ahmadi2
A Unified Synapse-Neuron Building Block for Hybrid VLSI
Neural Networks
H. Djahanshahi, W.C. Miller, M. Ahmadi and G.A. Jullien
University of Windsor, ON, CANADA
ahmadi@engn.uwindsor.ca
T4N42
A7616
1461_ccwang3
Hardware Implementation of Exponential Bidirectional
Associative Memory by Current-Mode Circuits
C.-C. Wang and J.-M. Wu
National Sun Yat-Sen University, Kaosiung, TAIWAN, ROC
ccwang@ee.nsysu.edu.tw
T4N43
A8611
0520_wolf
A New Genetic Single-Layer Routing Algorithm for Analog Transistor Arrays
H.G. Wolf and D.A. Mlynski
Universitat Karlsruhe, Karlsruhe, GERMANY
wolf@temds2.etec.uni-karlsruhe.de
T4N44
A8612
0839_wangpt
A Simultaneous Placement and Global Routing Algorithm for an FPGA
P.T. Wang and K.N. Chen
National Cheng Kung University, Taiwan, TAIWAN, ROC
wangs@cad8.cme.ncku.edu.tw
T4N45
A8613
0958_aetzel
An Iterative Approach to Hierarchical Wire Routing
A. Etzel
Daimler-Benz AG, Frankfurt, GERMANY
etzel@dbag.fra.daimlerbenz.com
T4N46
A8614
1114_okada
Global Routing Algorithm for Analog Circuits Using Register Array Model
K. Okada, H. Onodera and K. Tamaru
Kyoto University, Kyoto, JAPAN
okada@tamaru.kuee.kyoto-u.ac.jp
T4N47
A8615
2001
An efficient clustering technique for circuit partitioning
Areibi and Vannelli
University of Waterloo, Waterloo, CANADA
abk@cs.ucla.edu
T4N48
A8616
2005
A hybrid genetic algorithm for the channel routing problem
Gockel, Pudelko, Deschsler and Becker
Technical University of Frankfurt, Frankfurt, GERMANY
abk@cs.ucla.edu
T4N49
A8803--move to poster
1224_lfc2
Controller Power Estimation using Information from Behavioral Description
P. Surti and L.-F. Chao
Iowa State University, Ames, IA
lfc@iastate.edu
Banquet, Tuesday, May 14, 1996 (6:30pm to 9:00pm)
-------------------------------------------------
6:30pm to 7:00pm - Reception
7:00pm to 8:00pm - Dinner
8:00pm to 8:40pm - Sharon Kingman, "The 1996 Olympic Games - High Tech/High
Touch"
8:40pm to 9:15pm - Awards - Part II
Sharon Brock Kingman
National Sales Manager, Olympic Programs
BellSouth Business Systems
BIOGRAPHICAL SKETCH
Ms. Kingman has worked for Southern Bell, AT&T, and BellSouth since 1981 in
the Marketing area. She served as the National Account Manager for R.J.
Reynolds, Norfolk Southern, and Baxter Healthcare during this time. She
helped establish BellSouth's marketing direction for the 1996 Olympics in
Atlanta, Georgia working on sponsorship issues, promotions direction and
service offerings for the many customers that will be in Atlanta prior to
and during the event. She developed products and pricing to be offered to
the 2,000 plus customers in Atlanta for the Olympic and Paralympic Games.
Ms Kingman has worked with the Atlanta Committee for the Olympic Games
since 1989. She served as host to various IOC members as they came to
Atlanta to consider the bid for the 1996 Games. She was in Tokyo, Japan
for the announcement of Atlanta as the winner for the 1996 Olympic Games.
She now works full time planning the telecommunications aspects of the 1996
Olympic and 1996 Paralympic Games. Her role includes the development of
the video, data and voice networks for the Games.
She has spoken to many groups about the technical demands of the Olympic
Games, particularly in the area of communications. These groups include
Hewlett-Packard, Social Security Administration, and others. She will be
speaking at the IEEE Vehicular Technology Conference in early May, 1996.
She has gained a reputation of being an entertaining and informative
speaker on the subject of the 1996 Olympic Games.
Wednesday, 8:30 a.m. -- 10:00 a.m., Room A
W1A00
Session Title: Analog Signal Processing -- Transconductor Amplifiers
and Applications
Chair: W. Snelgrove
Carleton University, Ottawa, ON, CANADA
snelgar@doe.carleton.ca
W1A01
A1701
1182_blalock
A One-Volt, 120-uW, 1-MHz OTA for Standard Digital CMOS Technology
B. J. Blalock and P. E. Allen
Georgia Institute of Technology, Atlanta, GA
blalock@ee.gatech.edu
W1A02 --WITHDRAWN
A1702
0084_lsi1
Wide Range Linear Tunable BICMOS Transconductor and Four-Quadrant Multiplier
Shen-Iuan Liu
National Taiwan University, Taipei, TAIWAN, ROC
lsi@cc.ee.ntu.edu.tw
W1A03
A1703
0080_kuwait2
A BiCMOS with Applications to Highly Linear Analog Transconductor Realisations
N.I. Kachab, A.A.Al-Saquer and J.G. Varghese
Kuwait University, Khaladiya, KUWAIT
Khachab@eng.kuniv.edu.kw
W1A04
A1704
1115_omid
A Wide-Range Tunable 25MHz-110MHz BiCMOS Continuous-Time Filter
O. Shoaei and W. M. Snelgrove
Carleton University, Ottawa, ON, CANADA
omid@doe.carleton.ca
Wednesday, 8:30 a.m. -- 10:00 a.m., Room B
W1B00
Session Title: Analog VLSI Implementation I
Chair: Paul Furth, New Mexico State Univ.
pfurth@nmsu.edu
W1B01
A7701
0192_tsao
Subjective Motion Detector and its Analog VLSI Implementation
Y. Cao, B. Marholev, and S. Mattisson
Lund University, Lund, SWEDEN
tsao@tde.lth.se
W1B02
A7702
0007_akers3
A Habituation, Rehabituation, and Recovery Chip
V.K. Goru and L.A. Akers
Arizona State University, Tempe, AZ
lakers@asu.edu
W1B03
A7703
1117_pfurth
Cochlear Models Implemented With Linearized Transconductors
P.M. Furth and A.G. Andreou
New Mexico State University, Las Cruces, NM
Johns Hopkins University, Baltimore, MD
pfurth@nmsu.edu
W1B04
A7704
1295_han8613
A General Purpose Neuro-Image Processor Architecture
G. Han and E. Sanchez-Sinencio
Texas A&M University College Station, TX
han8613@amesp01.tamu.edu
Wednesday, 8:30 a.m. -- 10:00 a.m., Room C
W1C00
Session Title: Computer-Aided Design -- Physical Design
Chair: Howard Chen
IBM Research, Yorktown Heights, NY
W1C01
A8701
1031_abk3
Simple Eigenvector-Based Circuit Clustering Can Be Effective
C.J. Alpert and A.B. Kahng
University of California, Los Angeles, CA
abk@cs.ucla.edu
W1C02
A8702
0013_ball1
A Stochastic Neural Network Approach for Circuit Partitioning
C.F. Ball and D.A. Mlynski
University of Karlsruhe, GERMANY
ball@temds2.etec.uni-karlsruhe.de
W1C03
A8703
0366_banerjee
A Parallel Hierarchical Algorithm for Module Placement Based on
Sparse Linear Equations
Z. Xing and P. Banerjee
University of Illinois, Urbana, IL
banerjee@crhc.uiuc.edu
W1C04
A8704
0505_ross
Pin Assignment with Timing Consideration
T.W. Her
Mentor Graphics Corporation, San Jose, CA
ross_her@mentorg.com
Wednesday, 8:30 a.m. -- 10:00 a.m., Room D
W1D00
Session Title: Digital Signal Processing -- Adaptive Signal Processing II
Chair: Y. F. Huang
University of Notre Dame, IN
huang.2@nd.edu
W1D01
A2701
1136_willson3
A Simplified Signed Powers-of-Two Conversion for Multiplierless Adaptive Filters
C.-L. Chen, K.-Y. Khoo and A. N. Willson, Jr.
University of California, Los Angeles, CA
willson@icsl.ucla.edu
W1D02
A2702
0434_marianne
An Adaptive Filtering Subband Structure with Critical Sampling
A.P.R. Rodrigues, M.R. Petraglia and J. Szczupak
Federal University of Rio de Janiero, BRAZIL
Catholic University of Rio de Janiero, BRAZIL
mariane@coe.ufrj.br
W1D03
A2703
0017_bermudez
Stability of Non-Weiner Solutions of the Filtered-XLMS Algorithm
N.J. Bershad and J.C.M. Bermudez
University of California Irvine, Irvine, CA
University Federal de Santa Catarina, Florianopolis, SC, BRAZIL
bermudez@linse.ufsc.br
W1D04
A2704
0256_azimi
A Modified Block FTF Adaptive Algorithm with Applications
to Underwater Target Detection
M. A. Hasan, M. R. Azimi-Sadjadi and S. Charleston
Colorado State University, Fort Collins, CO
Universidad Autonoma Metropolitana, Mexico City, MEXICO
Azimi@lance.colostate.edu
Wednesday, 8:30 a.m. -- 10:00 a.m., Room E
W1E00
Session Title: Power Circuits and Systems -- Power System Dynamics and Control
Chair: V. Venkatasubramanian
Washington State University, Pullman, WA
mani@eecs.wsu.edu
W1E01
A5101
1299_mani
Complicated Chaos from Intermittency Mechanisms in a Simple Power System
V. Venkatasubramanian and W. Ji
Washington State University, Pullman, WA
mani@eecs.wsu.edu
W1E02
A5101
1448_kghosh
Hopf Bifurcations as Affected by Exciter, Load and SVC Dynamics in Power Systems
B.C. Pal
Jadavpur University, Calcutta, INDIA
kghosh@lwbbs.com
W1E03
A5101
1232_fekih
Necessary and Sufficient Conditions for Load Balance in Three-Phase Power Systems
L. Fekih-Ahmed
Schlumberger Industries, Montrouge, FRANCE
fekih@montrouge.em.slb.com
W1E04
A5101
1105_mhong
Complete Controllability Region of a Dynamic N-bus Power system
Model with Bounded Controls
C. C. Liu and M. Hong
University of Washington, Seattle, WA
liu@ee.washington.edu
Wednesday, 8:30 a.m. -- 10:00 a.m., Room F
W1F00
Session Title: Nonlinear Circuits & Systems -- Bifurcations and Chaos
Chairs: Guanrong Chen
University of Houston, Houston, TX
gchen@uh.edu
W1F01
A4701
0047_endoh
Bifurcation routes to chaos of 2-coupled oscillators and stabilization
of unstable periodic orbits embedded in the chaotic attractor
T. Endo and A. Hasegawa
Meiji University, Kawasaki, JAPAN
endoh@isc.meiji.ac.jp
W1F02
A4702
0794_gchenmoi
On the Birth of Multiple Limit Cycles in Nonlinear Systems
J.L. Moiola and G. Chen
Nacional Universidad del Sur, Bahia Blanca, ARGENTINA
University of Houston, TX
gchen@uh.edu
W1F03
A4703
0391_nakagawa
An RC OTA Hysteresis Chaos Generator
S. Nakagawa and T. Saito
Hosei University, Tokyo, JAPAN
nakagawa@toshi.ee.hosei.ac.jp
W1F04
A4704
0142_william
Bifurcation in Bifurcation from a Current-Programmed DC/DC Boost Converter
W. Chan and C. Tse
Hong Kong Polytechnic University, Hong Kong
william@encserver.en.polyu.edu.hk
Wednesday, 8:30 a.m. -- 10:00 a.m., Room G
W1G00
Session Title: VLSI Systems and Applications -- Cellular Applications
Chair: Sayfe Kiaei
Oregon State University
W1G01
A6701
0144_willson2
A Low-Power State-Sequential Viterbi Decoder for CDMA Digital
Cellular Applications
I. Kang and A. N. Willson, Jr.
University of California, Los Angeles, CA
willson@ee.ucla.edu
W1G02
A6702
0217_jihyun
Reverse Link Demodulator ASIC for CDMA Cellular System
J.I. Hyun, J.J. Cha, I. Kang, J. S. Kim and K. S. Kim
Electronics and Telecommunications Research Institute, Taejon, KOREA
jihyun@cadvax.etri.re.kr
W1G03
A6703
1303_hahm
Analog vs. Digital: A Comparison of Circuit Implementations for
Low-Power Matched Filters
M. D. Hahm, E. G. Friedman and E. L. Titlebaum
University of Rochester, Rochester, NY
hahm@ee.rochester.edu
W1G04
A6704
1249_boutillon
High Speed Low Power Architecture for Memory Management in a Viterbi Decoder
E. Boutillon and N. Demassieux
Ecole Nationale Superieure des Telecommunications, Paris, FRANCE
boutillon@elec.enst.fr
Wednesday, 8:30 a.m. -- 10:00 a.m., Room H
W1H00
Session Title: Visual Signal Processing -- VLSI for Video Signal Processing
Chair: Liang-Gee Chen
National Taiwan University, Taipei, TAIWAN, ROC
lgchen@video.ee.ntu.edu.tw
W1H01
A3701
1332_kobayashi_1
VLSI Implementation of the Complete Chip Set for MPEG2 Real-Time Encoder
T.Kobayashi, R.Saito, N.Nagai, J.Kimura, T.Nakatomi, H.Arai, T.Sakaguchi,
K.Goto, D.Wuertele, M.Sato, Y.Watatani, H.Fujiwara, H.Ootubo, K.Asada,
K.Matumoto and Y.Okada
Graphics Communication Laboratories, Shibuya-ku, Tokyo, JAPAN
Hitachi, Ltd., Yokohama-shi, Kanagawa, JAPAN
Hitachi, Ltd., Kokubunji-shi, Tokyo, JAPAN
koba@gctech.co.jp
W1H02
A3702
1173_onoe
A VLSI Architecture for MPEG2 MP@HL Real Time Motion Estimator
T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa and K. Matsumura
Osaka University, Suita, Osaka, JAPAN
KCS Co., Ltd., Higashi-Osaka, Osaka, JAPAN
onoe@ise.eng.osaka-u.ac.jp
W1H03
A3703
1297_qc00_lehigh
VLSI Implementation of Vector Quantization using Distributed Arithmetic
H. Q. Cao and W. Li
Lehigh University, Bethlehem, PA
qc00@pl122f.csee.lehigh.edu
W1H04
A3704
0121_shark
Finite Wordlength Effects Analysis and Wordlength Optimization of a
Multiplier-Adder Based 8x8 2D-IDCT Architecture
S. Kim and W. Sung
Seoul National University, Seoul, KOREA
wysung@hdtv.snu.ac.kr
Wednesday, 8:30 a.m. -- 10:00 a.m., Room N, Poster Sessions
W1N00
Session Title: Analog Signal Processing -- Analog Circuit Applications
Chair: P. Aronhime
University of Louisville, Louisville, KY, USA
pbaron01@homer.louisville.edu
W1N01
A1711
0537_meskiyerli
State-Space Synthesis of Biquads Based on the Mosfet Square Law
M.H. Eskiyerli, A.J. Payne and C. Toumazou
Imperial College, London, UK
m.eskiyerli@ic.ac.uk
W1N02
A1712
0700_leob
Wavelets Generation using Laguerre Analog Adaptive Filter
L. Ortiz-Balbuena, H. Perez-Meana, A. Martinez-Gonzalez and E. Sanchez-Sinencio
University Autonoma Metropolitana, Mexico City, MEXICO
Texas A & M University, College Station, TX
leob@xanum.uam.mx
W1N03
A1713
0002_adadum
The Influence of the MLP's Output Dimension on its Performance in
Image Restoration
A. Dumitras and V. Lazarescu
Polytechnica University of Bucharest, ROMANIA
adadum@vala.elia.pub.ro
W1N04
A1504
0096_nadi
An Oversampling Transconductance Amplifier Using Sampled-Data Feedback
N. Itani and T. Sculley
Crystal Semiconductor Corporation, Austin, TX
Washington State University, Pullman, WA
nadi@crystal.cirrus.com
W1N05
A1715
1606
Issues in the synthesis of voltage-, current-, and voltage-current mode circuits
Z.J. Lata, P.B. Aronhime, B.J. Maundy and J.M. Zurada
University of Louisville, Louisville, KY
pbaron01@homer.louisville.edu
W1N06
A1716
1034_chwang
A Universal Simple LV/LP OpAmp Input Stage with Programmable
Rail-to-Rail Constant-gm
C. Hwang, A. Motamed and M. Ismail
Ohio State University, Columbus, OH
chwang@ee.eng.ohio-state.edu
W1N06a
Session Title: Digital Signal Processing -- Filtering and Filter Design III
Chair: T. Saramaki
VLSI Solution Oy, Tampere, FINLAND
ts@cs.tut.fi
W1N07
A2711
0056_gck
Improved Algorithm To Design Weighted Minmax Quadrature Mirror Filters
C. K. Goh, Y. C. Lim and C. S. Ng
National University of Singapore, SINGAPORE
gck@vlsi.ee.nus.sg
W1N08
A2712
1080_karam
Design of Optimal Digital FIR Filters with Arbitrary Magnitude
and Phase Responses
L. Karam and J. McClellan
Arizona State University, Tempe, AZ
Georgia Technology, Atlanta, GA
karam@asu.edu
W1N09
A2713
1302_yuet_parhi
STAR RLS Lattice Adaptive Filters
Y. Li and K.K. Parhi
University of Minnesota, Minneapolis, MN
parhi@ee.umn.edu
W1N10
A2714
1493_lennarth2
Allpass and Lattice Bilinear Digital Ladder Filters
L. Harnefors, S. Signell and K. Mossberg
Malardalen Univ., Ericsson Radio Systems, Sweden
lennarth@ekc.kth.se
W1N11
A2715
0136_victor3
Methods to Design Low-Sensitivity Canonical Digital Filters
Using Impulse Response Data
V. E. DeBrunner, T. A. Tutunji and A. R. Corzine
University of Oklahoma, Norman, OK
vdebrunn@uoknor.edu
W1N12
A2716
0676_hasan3
Accurate Noise Compensation Technique for the Identification of
Multichannel AR Processes with Noise
Md. K. Hasan and T. Yahagi
Chiba University, Chiba-shi, JAPAN
hasan@icsj1.tj.chiba-u.ac.jp
W1N12a
Poster Session during Panel Discussion: Image Filtering
Wednesday 10:30 - 12:00
Chair: Guido M. Cortelazzo
Electronical Information Department, Padova, ITALY
corte@dei.unipd.it
W1N13
A3711
0741_krit
Modified Tree Structure for Transform Vector Quantization
K. Panusopone and K.R. Rao
University of Texas at Arlington, Arlington, TX
krit@dip.uta.edu
W1N14
A3712
0612_enhyuen
Quadtree Segmented Two-Dimensional predictive visual Pattern BTC Image Coding
H. Yuen, C.K. Li and W.C. Siu
Hong Kong Polytechnic University, Kowloon, HONG KONG
enhyuen@hkpu01.polyu.edu.hk
W1N15
A3713
0251_pei3
A Novel Block Truncation Coding of Color Images by Using
Quaternion-Moment-Preserving Principle
S. Pei and C. Cheng
National Taiwan University, Taipei, TAIWAN, ROC
pei@cc.ee.ntu.edu.tw
W1N16
A3714
0518_nguyen
Document Image Compression by Subband System
C.W. Kok and T.G. Nguyen
University of Wisconsin, Madison, WI
nguyen@ece.wisc.edu
W1N17
A3715
0631_osamakl
Restoration of Lossy Compressed Noisy Images
O.K. Al-Shaykh and R.M. Mersereau
Georgia Institute of Technology, Atlanta, GA
osamakl@eedsp.gatech.edu
W1N18
1341_tanaka
Self-Synchronization of analog PLLs in Communication Networks
H.-A. Tanaka and S. Oishi
Waseda University, Shinjuku-ku, Tokyo, JAPAN
tanaka@oishi.info.waseda.ac.jp
W1N19
A4711
0501_pastore
Capturing All Admissable Linear Regions For Fastening Simulation of
Piecewise-Linear Dynamic Circuits
S. Pastore and A. Premoli
University di Trieste, Trieste, ITALY
pastore@univ.trieste.it
W1N20
A4712
1148_tsubone
Stabilizing High-Period Orbits and Generation of Islands:
A Piecewise Linear Approach
T.Tsubone, K.Mitsubori and T.Saito
Hosei UniversityKoganei-shi,Tokyo,JAPAN
tsubone@toshi.ee.hosei.ac.jp
W1N21
A4713
0298_taylor
Piecewise Linear Methods for Digital Control of Input-Switched PWM Systems
M. Al-Numay and D. G. Taylor
Georgia Institute of Technology, Atlanta, GA
david.taylor@ece.gatech.edu
W1N22
A4714
0574_mhaydt
Piecewise Models for Noise Analysis of Digital CMOS Circuits
M.S. Haydt and S. Mourad
Santa Clara University, Santa Clara, CA
mhaydt@scuacc.scu.edu
W1N23
A4715
1055_harris
A subthreshold CMOS chaotic Oscillator
J.E. Neeley and J.G. Harris
University of Florida, Gainesville, FL
harris@knicks.ee.ufl.edu
W1N24
A4716
1213_benedetti
Tracing Characteristics of Smooth Nonlinear Resistive Circuits by
Interval Analysis
A. Benedetti and N. Guglielmi
Universita` degli Studi di Modena, ITALY
Universita` degli Studi di Trieste, ITALY
benedett@dsi.unimo.it
W1N24a
Session Title: Power Circuits and Systems -- Power Systems I
Chair: H. Mori
Meiji University, JAPAN
hmori@isc.meiji.ac.jp
W1N25
A5101
1165_hmori
Neuro Computing for State Estimation in Power Systems
H. Mori
Meiji University, JAPAN
hmori@isc.meiji.ac.jp
W1N26 -- WITHDRAWN; not in proceedings
A5101
0150_yilu
Neural Network for Transformer Fault Diagnosis
Y. Zhang, X. Ding, Y. Liu and P. J. Griffin
Virginia Tech, Blacksburg, VA
Doble Engineering Company, Watertown, MA
Yilu@vt.edu
W1N27
A5101
1158_wing_bchow
Static Var Compensator Control in Multi-Machine Power Systems
Using a quantized Controller
B.H. Chowdhury, B.M. Wilamowski and W.-C. Ma
University of Wyoming, Laramie, WY
bchow@uwyo.edu
W1N28
A5101
0876_malkiha
A Fuzzy Logic Controller for Boiler Systems in Power Plants
H.A. Malki and G. Chen
University of Houston, Houston, TX
malki@uh.edu
W1N29
A5101
1358_flueck
Solving the Nonlinear Power Flow Equations with a Newton Process and GMRES
A.J. Flueck and H-D. Chiang
Cornell University, Ithaca, NY
flueck@ee.cornell.edu
W1N30
A5101
1065_janko
Power System Contingency Analysis - An Improved Technique based
on Tellegen Theorem
R. Golob and F. Gubina
University of Ljubljana, Ljubljana, SLOVENIA
robert@lddees.fer.uni-lj.si
W1N31
A6711
0306_pihl
Automated Logic Synthesis with the CDPD Circuit Technique
J. Pihl and E.J Aas
Norwegian Institute of Technology, Trondheim, NORWAY
pihl@fysel.unit.no
W1N32
A6712
0567_andywu
Low Power Design Methodology for DSP Systems Using Multirate Approach
A.Y. Wu, K.J.R. Liu, Z. Zhang, K. Nakajima, A. Raghupathy and S.C. Liu
University of Maryland, College Park, MD
andywu@aloft.att.com
W1N33
A6713
0859_hyhuang2
True-Single-Phase All-N-Logic Differential Logic(TADL) for
Very High-Speed Complex VLSI
H.Y. Huang, Y.H. Chu, K.H. Cheng and C.Y. Wu
CCL, ITRI, TAIWAN, ROC
Tam-Kang University, TAIWAN, ROC
Chiao-Tung University, TAIWAN, ROC
HYHUANG@U1SUN13.CCL.ITRI.ORG.TW
W1N34
A6714
0860_hyhuang3
Feedback-Controlled Split-Path CMOS Buffer
H.Y. Huang and Y.H. Chu
CCL, ITRI, TAIWAN, ROC
HYHUANG@U1SUN13.CCL.ITRI.ORG.TW
W1N35
A6715
0890_hwangyt
A New Design Approach and VLSI Implementations of Recursive Digital Filters
C.-L. Sue and Y.-T. Hwang
National Yunlin Institute of Technology,Touliu, TAIWAN, ROC
hwangyt@cad.el.yuntech.edu.tw
W1N36
A6716
1133_spetsa
Structural Cell-based VLSI Circuit Design using a Genetic Algorithm
T. Arslan, D.H. Horrocks and E. Ozdemir
University of Wales College of Cardiff, Cardiff, UK
arslan@cardiff.ac.uk
W1N36a
Session Title: Neural Systems and Applications -- Analog VLSI Implementation II
Chair: B. Linares-Barranco
National Microelectronics Center, Sevilla, SPAIN
bernabe@cnm.us.es
W1N37
A7711
0416_csipty
On the Optimal Design of T-Norm and T-Conorm Based Fuzzy Weighted
Order Statistic Filters with Neural Learning in the Application
of Image Processing
P.-T. Yu and Y.-C. Hsia
National Chung Cheng University Chiayi, TAIWAN, ROC
csipty@ccunix.ccu.edu.tw
W1N38
A7712
0607_ccwang2
Hardware Realization of Multi-Valued Exponential Bidirectional Associative
Memory Using Current-Mode Circuits
C.-C. Wang and Y.-C. Chen
National Sun Yat-Sen University, Kaohsiung, TAIWAN, ROC
ccwang@ee.nsysu.edu.tw
W1N39
A7713
1044_espejo
Hybrid-Control of Synapse Circuits for Programmable Cellular Neural Networks
S. Espejo, R. Dominguez-Castro, R. Carmona and A. Rodriguez-Vazquez
University de Sevilla, Sevilla, SPAIN.
espejo@cnm.us.es
W1N40
A5904
0649_bdliu2
Current-Mode Fuzzy Linguistic Hedge Circuit - Contrast Intensification
C.Y. Chen, C.Y. Huang and B.D. Liu
National Cheng Kung University, Taiwan, TAIWAN, ROC
bdliu@cad8.cme.ncku.edu.tw
W1N41
A7715
0844_nishio2
Breakdown of In-Phase Synchronization of Two Chaotic Circuits
Coupled by an Inductor
M. Wada, Y. Nishio and A. Ushida
Tokushima University, Tokushima, JAPAN
wada@ee.tokushima-u.ac.jp
W1N42
A7716
1259_apa
High Speed 16 by 16 CNN Chip
A. Paasio, A. Dawidsiuk, K. Halonen and V. Porra
Helsinki University of Technology, Espoo, FINLAND
apa@clara.hut.fi
W1N43
A8711
0209_casinovi
A Multi-Level Simulator with Analog Behavioral Models
G. Casinovi and J.M. Yang
Georgia Institute of Technology, Atlanta, GA
giorgio.casinovi@ee.gatech.edu
W1N44
A8712
0419_bucher
Accurate MOS Modelling for Analog Circuit Simulation Using the EKV Model
M. Bucher, C. Lallement, C.C. Enz and F. Krummenacher
Swiss Federal Institute of Technology, Lausanne, SWITZERLAND
bucher@leg.de.epfl.ch
W1N45
A8713
0563_h.su
An Interactive Visualization Tool for Analog Design
H. Su, H. Dawkes, L.Tweedie and R. Spence
Imperial College, London, UK
h.su@ic.ac.uk
W1N46
A8714
1111_musil
Simulation of the Test Process for Analogue Integrated Circuits
J. Povazanec and V. Musil
Leeds Metropolitan University, Leeds, UK
Technical University of Brno, Brno, CZECH REPUBLIC
j.povazanec@lmu.ac.uk
W1N47
A8715
1162_xavierh
A Design, Simulation and Synthesis Tool for Delta-Sigma-Modulator-Based
Signal Sources
X. Haurie and G. W. Roberts
McGill University, Montreal, CANADA
roberts@macs.ee.mcgill.ca
W1N48
A8716
1903
On The Symbolic Calculation of Nonlinear Circuits
Ralf Sommer, Eckhard Hennig and Andreas Dittrich
Universitaet Kaiserslautern, GERMANY
rsommer@rhrk.uni-kl.de
huelsman@ece.arizona.edu
marwan@iastate.edu
Wednesday, 10:30 a.m. -- 12:00 p.m., Room A
W2A00
Session Title: Panel on Future of Analog Signal Processing
Organizer and Chair: Gordon W. Roberts
McGill University
roberts@macs.ee.mcgill.ca
"Analog Systems for Multi-Media"
Prof. Mohammed Ismail, Ohio State University
ismail@ee.eng.ohio-state.edu
"Delta-Sigma Modulation"
Prof. Martin Snelgrove, Carleton University
snelgar@doe.carleton.ca
"Mixed-Signal Testing"
Prof. Ken Laker, University of Pennsylvania
laker@pender.ee.upenn.edu
"RF Circuits"
Prof. Bosco Leung, University of Waterloo
bleung@sun14.vlsi.uwaterloo.ca
"CAD For Analog Circuits"
Prof. John Sewell, University of Glasgow
sewell@elec.gla.ac.uk
Wednesday, 10:30 a.m. -- 12:00 p.m., Room B
W2B00
Session Title: Panel on Neural Networks (merged with VLSI in Room G)
Wednesday, 10:30 a.m. -- 12:00 p.m., Room C
W2C00
Session Title: Panel on Future of Computer-Aided Design
Chair: D. F. Wong
University of Texas, Austin, TX
wong@cs.utexas.edu
Panelists:
Prof. Chung-Kuan Cheng, University of California, San Diego, CA
Prof. Rajesh Gupta, University of Illinois, Urbana-Champaign, IL
Prof. Andrew B. Kahng, University of California, Los Angeles, CA
Prof. Hidetoshi Onodera, Kyoto University, Kyoto, JAPAN
Prof. Kaushik Roy, Purdue University, West Lafayette, IN
Prof. Daniel Saab, Case Western Reserve University, Cleveland, OH
Wednesday, 10:30 a.m. -- 12:00 p.m., Room D
W2D00
Session Title: Digital Signal Processing -- Multirate and Filter Banks III
Chair: P. P. Vaidynathan
California Institute of Technology, Pasadena, CA
ppvnath@sys.caltech.edu
W2D01
A2201
1410_jugo
Approximate Moments and Regularity of Efficiently Implemented
Orthogonal Wavelet Transforms
J. Gotze, J.E. Odegard, P. Reider and C.S. Burrus
Rice University, Houston, TX
jugo@ece.rice.edu
W2D02
A2202
0060_hboelcsk2
Frame-Theoretic Analysis and Design of Oversampled Filter Banks
H. Boelcskei, F. Hlawatsch and Hans G. Feichtinger
Vienna University of Technology, Vienna, AUSTRIA
hboelcsk@aurora.nt.tuwien.ac.at
bolcskei@natlab.research.philips.com
W2D03
A2203
0107_ppvnath2
New Results on Paraunitory Filter Banks Over Finite Fields
S. M. Phoong and P. P. Vaidyanathan
California Institute of Technology, Pasadena, CA
ppvnath@sys.caltech.edu
W2D04
A2204
0322_bxuan
Complete FIR Principal Component Filter Banks
B. Xuan and R. Bamberger
Washington State University, Pullman, WA
bamberg@eecs.wsu.edu
Wednesday, 10:30 a.m. -- 11:15 p.m., Room E
W2E00
Session Title: Panel on the Future of Power Circuits
Chair: M. Kazimierczuk, Universita' di Modena, Modena, ITALY
10:30-10:45
Magnetics
Alberto Reatti
10:45-11:00
Simulation of Power Electronics Circuits
Antonio Massarini
11:00-11:15
Chaos in Power Electronics Circuits
L. Fortuna
11:15-11:30
Switched-Capacitor Converters
Adrian Ioinovici
11:30-11:45
Control Aspects in Power Electronics
Spiazi
11:45-12:00
Soft-Switching Rectifiers
J. Uceda
Wednesday, 11:15 a.m. - 12:00 p.m., Room E
Session Title: Overview of Power Systems II
Chair: H. Mori, Meiji University, Kawasaki, JAPAN
Speaker: H. Mori, Meiji University, Kawasaki, JAPAN
Title: Overview on Aritificial Neural Network in Power Systems
Wednesday, 10:30 a.m. -- 12:00 p.m., Room F
W2F00
Session Title: NONE
Wednesday, 10:30 a.m. -- 12:00 p.m., Room G
W2G00
Session Title: Panel for VLSI and Neural Systems --
Can CAS Research Play a Big Role in Multimedia Market? How Big?
Organizers and Moderators:
Bing Sheu, University of Southern California
Chung-Sheng Li, IBM T. J. Watson Center
Panelists:
Prof. Ming Liou, Hong Kong University of Science and Technology
"Current and Future Involvements by CAS Researchers"
Prof. Rui Defigueiredo, University of California at Irvine
"Image Processing & Machine Vision for
Telerobotics, Medical Applications, Health-Care Delivery"
Dr. HorngDar Lin, AT&T Bell Labs.
"Areas Need More Attention by CAS Researchers/Engineers"
Dr. Takao Nishitani, NEC Research Lab.
"Multimedia Activities in Japan and Far East"
Prof. Andreas Andreou, John Hopkins University
"Human Interface Support, Especially Speech"
Dr. Chung-Sheng Li, IBM T. J. Watson Center
"Content-Based Retrieval for Multimedia Database"
Prof. Mohammed Ismail, Ohio State University
"Low Power ICs for Wireless Communication"
Wednesday, 10:30 a.m. -- 12:00 p.m., Room H
W2H00
Title: The future of image coding: What will be new?
Organizer and chair: Joern Ostermann, AT&T Bell Laboratories, Holmdel, NJ
Panel:
Mike Orchard, Princeton University
Alan Sloan, Iterated Systems
Alex Pentland, MIT, Media Lab
Eric Petajan, AT&T Bell Laboratories
Ya-Qin Zhang, David sarnoff Research Center
Ali Tabatabai, Tektronix
Wednesday, 8:30 a.m. -- 10:00 a.m., Room N, Poster Sessions
W2N00
Session Title: Analog Signal Processing -- Analog Circuit Application I
Chair: P. Aronhime
University of Louisville, Louisville, KY, USA
pbaron01@homer.louisville.edu
W2N01
A1011
1601
Switch-capacitor current conveyor building blocks
B. J. Maundy and P. B. Aronhime
University of Louisville, Louisville, KY, USA
pbaron01@homer.louisville.edu
W2N02
A1012
1602
Temperature-stable voltage-to-frequency converters
Sean Sidong Cai and Igor M. Filanovsky
University of Alberta, Edmonton, CANADA
pbaron01@homer.louisville.edu
W2N03
A1013
1603
An experimental, ultra-high-Q, VHF receiver front-end
William B. Kuhn, F. William Stephenson and Aicha Elshabini-Riad
Virginia Polytechnic Institute and State University, Blacksburg, VA
ariad@vtvm1.cc.vt.edu
pbaron01@homer.louisville.edu
W2N04
A1014
1604
A simple 6-bit neural based A/D converter employing only CMOS inverters
Cong-Kha Pham, Mamoru Tanaka and Katsufusa Shono
Sophia University, Tokyo, JAPAN
pbaron01@homer.louisville.edu
W2N05
A1015
1605
Issues in the design of analog BiCMOS integrated circuits
Frode Larsen and M. Ismail
AT & T Bell Labs, Allentown, PA
Ohio State University, Columbus, OH
pbaron01@homer.louisville.edu
W2N06
A1016
1607
New network theorems for current-mode circuit design
KeChang Wang, P.B. Aronhime and Mejul Desai
University of Louisville, Louisville, KY
pbaron01@homer.louisville.edu
W2N06a
Session Title: Digital Signal Processing -- Multidimensional Signal Processing
Chair: Y. C. Lim
National University of Singapore, SINGAPORE
lelimyc@ee.nus.sg
W2N07
A3401
0147_xiao1
Discrete-Time Lossless Bounded Real Lemma for
Multidimensional Separable Denominator Digital Systems
C. Xiao and D. J. Hill
University of Sydney, Sydney, NSW, AUSTRALIA
xiao@ee.su.oz.au
W2N08
A3404
0148_xiao2
Design of 2-D Linear Phase IIR Digital Filters Using 2-D
Impulse Response Gramians and Implementation with Low
Roundoff Noise and No Overflow Oscillations
C. Xiao and P. Agathoklis
University of Sydney, Sydney, NSW, AUSTRALIA
University of Victoria, Victoria, BC, CANADA
xiao@ee.su.oz.au
W2N09
A3402
0033_deng
Parallel Realization Method for Multidimensional Digital Filters
T.-B.Deng and A.Saito
Toho University, Funabashi, Chiba, JAPAN
deng@toho-u.ac.jp
W2N09a
Session Title: Digital Signal Processing -- High Fidelity Data Compression II
Chairs: N. Magotra, G. Mandyam and S. Stearns
University of New Mexico, Albuquerque, NM
magotra@unm.edu
gmandyam@eece.unm.edu
Sandia National Laboratories, Albuquerque, NM
sdstear@sandia.gov
W2N10
A2014
2305
A multiple transform based scheme for still color image compression
Arun Ramaswamy and Wasfy B. Mikhael
University of Central Florida, Orlando, FL
wbm@engr.ucf.edu
W2N11
A2015
2302
Fidelity enhancement of transform based image coding using
non-orthogonal basis images
Albert P. Berg and Wasfy B. Mikhael
Lockheed-Martin Corp., Orlando, FL
University of Central Florida, Orlando, FL
aberg@dspsparc.engr.ucf.edu
wbm@engr.ucf.edu
W2N12
A2016
2307
Lossless Compression of Synthetic Aperture Radar Images
R.W. Ives, Neeraj Magotra and Giridhar Mandyam
gmandyam@eece.unm.edu
magotra@unm.edu
W2N13
A3011
0195_bruton2
A Real-Time Video Implementation of a Three-Dimensional First-Order
Recursive Discrete-Time Filter
C. Kulach, L. Bruton, and N. Bartley
University of Calgary, Alberta, CANADA
bruton@enel.ucalgary.ca
W2N14
A3012
0542_jenkins
Fast Two-Dimensional Adaptive IIR Algorithms
R. Soni and W. K. Jenkins
University of Illinois at Urbana-Champaign, IL
jenkins@uicsl.csl.uiuc.edu
W2N15
A3013
0506_omair
A Least-Square Solution to the Design Problem of 2-D Linear-Phase
FIR Filters with Arbitrary Magnitude Responses
W.P. Zhu, M.O. Ahmad and M.N.S. Swamy
Nanjing University, Nanjing, CHINA
Concordia University, Montreal, CANADA
omair@ece.concordia.ca
W2N16
A3014
0267_tavsanav
Multiscale Edge Detection using IIR Filter Banks
E. Tufan and V. Tavsanoglu
South Bank University, London, UK
tavsanav@vax.sbu.ac.uk
W2N17
A3015
0151_youngin
Model and Optimal Filtering of Linearly-Additive Spatially-Invariant
Continuous-Measurement Imaging
Y. Oh and J.B. Farison
Electronics and Telecommunications Research Institute, Taejon, KOREA
University of Toledo, Toledo, OH
youngin@logos.etri.re.kr
W2N18
A3016
0922_furukawa2
A Fast Adaptive Algorithm Based on the Gradient Method for the Reduction
of the Computational Requirements
S. Yoshimoto, Y. Kitano and T. Furukawa
Fukuoka Institute of Technology, JAPAN
kitano@csl.sony.co.jp
W2N19
A4011
1261_varrientos
On the Monolithic Design of Hysteretic Chaotic Oscillators
J.E. Varrientos and E. Sanchez-Sinencio
Texas A & M University, College Station, TX
j-varrientos@tamu.edu
W2N20
A4012
1480_ibbini
Robust Pole Assignment: Conventional and Entropy/H Approaches
M. Ibbini and M. AL-Zoubi
Jordan University of Science and Technology, Irbid, JORDAN
mkha@amra.nic.gov.jo
W2N21
A4013
0365_eswaran
Rational Interpolation in H-Infinity with a Posteriori Error Bounds
Mailachalam Babu and Chikkannan Eswaran
Indian Institute of Tech., Madras, INDIA
eswaran@eedpt3.iitm.ernet.in
W2N22
A4014
0914_braiek
Non-Linear Stabilizing Control of Synchronous Electrical Machines
E. Benhadj Braiek
Ecole Nat. d'Ing., Tunis, TUNISIA
W2N23
A4015
0302_mirzai
Upper Bounds for Robustness of CNN Templates and a Design Approach for
Robust Templates
B. Mirzai and G.S. Moschytz
Swiss Federal Institute of Technology, Zurich, SWITZERLAND
mirzai@isi.ee.ethz.ch
W2N24
A4016
0814_tetsushi
Unstable Saddle-Node Connecting Orbits in the Averaged Duffing-Rayleigh Equation
T. Ueta and H. Kawakami
University of Tokushima, Tokushima, JAPAN
tetsushi@is.tokushima-u.ac.jp
W2N24a
Session Title: Power Circuits and Systems -- Power Systems II
Chair: M. M. Becovic
Georgia Institute of Technology, Atlanta, GA
W2N25
A5101
0540_mmadriga
Power Circuits Analysis in the Real Harmonic Hartley Domain
M. Madrigal and S. Acha
Nuevo Leon University, Monterrey, N.L., MEXICO
ad786011@gama.fime.uanl.mx
W2N26
A5101
0850_fukuyamay
Parallel Power Flow Calculation in Electric Distribution Networks
Y. Fukuyama, Y. Nakanishi and H.D. Chiang
Fuji Electric Co. R & D, Tokyo, JAPAN
Cornell University, Ithaca, NY
FCN02384@niftyserve.or.jp
W2N27
A5101
1004_abur
Determining Optimal Radial Network Topology within the Line Flow Constraints
A. Abur
Texas A & M University, College Station, TX
abur@eesun1.tamu.edu
W2N28
A5101
1081_ey1
Adaptive Prediction of Harmonic Signals in Electric Power Systems
J. Amirazodi, E.E. Yaz and K.J. Olejniczak
University of Arkansas, Fayetteville, AR
ey1@engr.uark.edu
W2N29
A5101
1280_gubinaf
Voltage Collapse Proximity in the Case of Radial Network
B. Strmcnik and F. Gubina
University of Ljubljana, Ljubljana, SLOVENIA
gubinaf@lddees.fer.uni-lj.si
W2N30
A5101
0243_sjhuang1
A Method of Supervising Power System Harmonic Trends
S.-J. Huang, C.-L. Huang and C.-T. Hsieh
Kaohsiung Polytechnic Institute, TAIWAN, ROC
National Cheng-Kung University, Taiwan, TAIWAN, ROC
clhuang@mail.ncku.edu.tw
W2N31
A5101
0375_mb50
Power System Disturbance Monitoring Using Spectral Analysis
M. Begovic and P. Djuric
Georgia Institute of Technology, Atlanta, GA
State University of New York at Stony Brook, NY
miroslav@power.ee.gatech.edu
W2N32
A6011
1339_ccsu_ncu_tw
A New VSB Modulation Technique and Shaping Filter Design
S.C. Yin, C.C. Su, M.T. Shiue, L.Y. Huang, C.K. Wang and W.I. Way
National Central University, Chung-Li, TAIWAN, ROC
National Chiao Tung University, Hsinchu, TAIWAN, ROC
ccsu@mbox.ee.ncu.edu.tw
W2N33
A6012
1514_kneip
Parallel Implementation of Medium Level Algorithms on a
Monolithic ASIMD Multiprocesor
J. Kneip, M. Ohmacht, J. Wittenburg and P. Pirsch
University of Hannover, GERMANY
kneip@scoop.mst.uni-hannover.de
W2N34
A6013
0323_roy
A VLSI System Implementation for Real-Time Object Detection
R. W. Melton, T. C. Huang, C. O. Alford and L. Becker
Georgia Institute of Technology, Atlanta, GA
U.S. Army Space & Strategic Defense Command, Huntsville, AL
roy@cerl.gatech.edu
W2N35
A6014
0383_petriec
Modeling and Simulation of Oscillator-Based Random Number Generators
C. S. Petrie and J. A. Connelly
Georgia Institute of Technology, Atlanta, GA
connelly@ee.gatech.edu
W2N36
A6015
0944_cylee
A Cost-Effective VLSI Architecture for High-Throughput Sequential Decoder
C.-Y. Lee
National Chiao Tung University, Hsinchu, TAIWAN, ROC
cylee@cc.nctu.edu.tw
W2N37
A6016
0508_lulik
An Eight Bit Adjustable Modulo Multiplier
S. Thomsen and A. Albicki
University of Rochester, Rochester, NY
lulik@ee.rochester.edu
W2N37a
Session Title: Neural Systems and Applications -- Applications III
Chair: Joseph E. Varrientos
Texas A & M University, College Station, TX
j-varrientos@tamu.edu
W2N38
A7011
1485_nwei2
A Neural Network Approach to Fault Diagnosis in Analog Circuits
N. Wei, S. Yang and S. Tong
Tsinghua University, Beijing, CHINA
dauywd@tsinghua.edu.cn
W2N39
A7012
1348_kschen
Multilayer Perceptron Neural Networks for Active Noise Cancellation
C. Chen and T-D. Chiueh
National Taiwan University, Taipei, Taiwan
kschen@vlsi.ee.hwh.edu.tw
W2N40
A7013
0756_hideasai3
Neuro-Based Tiling Algorithm Using Fitting Violation Function of Polyominoes
T. Nakayama, H. Ninomiya and H. Asai
Shizuoka University Hamamatsu, JAPAN
hideasai@eng.shizuoka.ac.jp
W2N41
A7014
0760_piazzaf3
Causal Back Propagation Through Time for Locally Recurrent Neural Networks
P. Campolucci, A. Uncini and F. Piazza
University of Ancona, Ancona, ITALY
paolo@eealab.unian.it
paolo@ucsd.edu
W2N42
A7015
0403_benedikt
Optimized Combination of Neural Networks
J.A.Benediktsson, J.R. Sveinsson, O.K. Ersoy and P.H. Swain
University of Iceland, Reykjavik, ICELAND
Purdue University, West Lafayette, IN
benedikt@verk.hi.is
W2N43
A7016
0791_wud
Reinforcement Learning for Electron Beam Steering
D. Wu
Stanford University, San Jose, CA
wud@engmail.ulinear.com
W2N44
1553
A Reconfigurable Parallel Inference Processor for High Speed Fuzzy Systems
D.A. Campbell
LaTrobe University, Bundoora, Victoria AUSTRALIA
D.Campbell@ee.latrobe.edu.au
W2N45
A8011
0010_aopal
Simulation of Oversampled Sigma Delta Converters
A. Opal
University of Waterloo, Waterloo, ON, CANADA
aopal@uwaterloo.ca
W2N46
A8012
0401_ero
Physical MOSFET's Model for Analog Circuit Design:
Application to Current Copier Based Architectures
E. Robilliart and E. Dubois
IEMN/ISEN, Cedex, FRANCE
ero@isen.fr
W2N47
A8013
0845_hkunieda
Translation of Specifications in Hierarchical Analog LSI Design
A.F. MasÕud, T. Ohtsuka and H. Kunieda
Tokyo Institute of Technology, Meguro-ku, Tokyo, JAPAN
hkunieda@ss.titech.ac.jp
W2N48
A8014
1308_leung_fychang
Wavelet-based Waveform Relaxation Simulation of Lossy Transmission Lines
W.H. Leung and F.Y. Chang
The Chinese University of Hong Kong, HONG KONG
fychang@ee.cuhk.hk
W2N49
A8015
1316_atdavis
Acceleration of Analog Simulation by Partial LU Decomposition
A. Davis
Rochester Institute of Technology, Rochester, NY
atd@cs.rit.edu
W2N50
0595_pjongan1
Improvement and Application of the Orientational Filter for Texture Image Analysis
P. Jongan
Chosun University, Kwangju, KOREA
pjongan@chollian.dacom.co.kr
Wednesday, 1:30 p.m. -- 3:00 p.m., Room A
W3A00
Session Title: Analog Signal Processing -- Sensors and Circuits
Chair: Al Connelly
Georgia Institute of Technology, Atlanta, GA
connelly@ee.gatech.edu
W3A01
A1801
0385_sandage
Producing Phototransistors in a Standard Digital CMOS Technology
R. W. Sandage and J. A. Connelly
Georgia Institute of Technology, Atlanta, GA
connelly@ee.gatech.edu
W3A02
A1802
0103_pardo
Response properties of a foveated space-variant CMOS image Sensor
F. Pardo, J.A. Boluda, J.J. Perez, S. Felici, B. Dierickx and D. Scheffer
Instituto de Robotica - Universidad de Valencia, Valencia, SPAIN
IMEC, Leuven, BELGIUM
Fernando.Pardo@uv.es
W3A03
A1803
1191_haeberli
CMOS Integration of a Thermal Pressure Sensor System
A. Haeberli, O. Paul, P. Malcovati, M. Faccio, F. Maloberti and H. Baltes
ETH Zurich, Zurich, SWITZERLAND
University of Pavia, ITALY
University of L'Aquila, ITALY
andreas@iqe.phys.ethz.ch
W3A04
A1804
1257_grigorie
A Circuit for the Temperature Compensation of Capacitive Sensors
M. Grigorie and F.Krummenacher
Swiss Federal Institute of Technology, Laussanne, SWITZERLAND
grigorie@leg.de.epfl.ch
Wednesday, 1:30 p.m. -- 3:00 p.m., Room B
W3B00
Session Title: Neural Systems and Applications -- Neural Network Applications
Chair: Mona Zaghloul
George Washington University, Washington, DC
zaghloul@seas.gwu.edu
W3B01
A7801
2701
A multi-dimensional analog gaussian radial basis circuit
L.A Akers, and Luke Theogarajan
Arizona State University, Tempe, AZ
newcomb@eng.umd.edu
lakers@asu.edu
W3B02
A7802
2705
An adaptive neuron model employing current-mode circuits and
its application to a dynamical neural network
Tsutomu Miki and Takeshi Yamakawa
Kyushu Inst. of Technology, Iizuka, JAPAN
newcomb@eng.umd.edu
yamakawa@ces.kyutech.ac.jp
W3B03
A7803
2702
Spaciotemporal neural networks for link-state routing protocols
Jack L. Meador
Washington State University, Pullman, WA
meador@eecs.wsu.edu
newcomb@eng.umd.edu
W3B04
A7804
2704
1-D compact neural networks for wireless communication and speech processing
Bing J. Sheu, David C. Chen and Eric Y. Chou
University of Southern California, Los Angeles, CA
sheu@pacific.usc.edu
newcomb@eng.umd.edu
Wednesday, 1:30 p.m. -- 3:00 p.m., Room C
W3C00
Session Title: Computer-Aided Design -- CAD for Low Power
Chair: Daniel Saab
Case Western Reserve University, Cleveland, OH
saab@alpha.ces.cwru.edu
W3C01
A8801
1060_hirata
Estimation of Short-Circuit Power Dissipation and its Influence on
Propagation Delay for Static CMOS Gates
A. Hirata, H. Onodera and K. Tamaru
Kyoto University, Kyoto, JAPAN
hirata@kuee.kyoto-u.ac.jp
W3C02
A8802
1000_wrzyszcz
Design of Parallel Synchronous Controllers for Low-power Applications
A. Wrzyszcz, D. Milford and E.L. Dagless
University of Bristol, Bristol, UK
A.Wrzyszcz@bristol.ac.uk
W3C03
1554
Exploiting Skewed State Probabilities for Low Power State Assignment
L. Bhupathi and L.-F. Chao
Iowa State University, Ames, IA
lfc@iastate.edu
W3C04
A8804
1033_kaushik
Maximum Power Estimation for CMOS Circuits Under Arbitrary Delay Model
C.Wang, T.Chou and K.Roy
Purdue University, West Lafayette, IN
Kaushik@ecn.purdue.edu
Wednesday, 1:30 p.m. -- 3:00 p.m., Room D
W3D00
Session Title: Digital Signal Processing -- Transforms and Transform Coding II
Chair: K. Egiazarian
Tampere University of Technology, Tampere, FINLAND
karen@cs.tut.fi
W3D01
A2801
0404_karen1
Generalizes Fibonacci Cubes and Trees for DSP Applications
K.O. Egiazarian and J.T. Astola
Tampere University of Technology, Tampere, FINLAND
karen@cs.tut.fi
W3D02
A2802
1351_nspencer_yuri
Convergence Analysis of Stochastically-Constrained Sample
Matrix Inversion Algorithms
Y.I. Abramovich, A.Y. Gorokhov and N.K. Spencer
CSSIP, Adelaide, SA, AUSTRALIA
Telecom Paris Department SIGNAL, Paris, FRANCE
yuri@cssip.edu.au
W3D03
A2803
1356_blandd
Analysis of Algorithms for a Non-Uniform Discrete Fourier Transform
D.M. Bland, T.I. Laakso and A. Tarczynski
University of Westminster, London, UK
blandd@wmin.ac.uk
W3D04
A2804
1452_koczy
Multi-Sine Synthesis and Analysis via Walsh-Hadamard Transformation
A.R. Varkonyi-Koczy
Technical University of Budapest, Budapest, HUNGARY
koczy@mmt.bme.hu
Wednesday, 1:30 p.m. -- 3:00 p.m., Room E
W3E00
Session Title: Analog Signal Processing -- Analog Building Blocks II
Chair: Ramesh Harjani
University of Minnesota, MN
harjani@ee.umn.edu
W3E01
A5801
1376_holman
A New Temperature Compensation Technique for Bandgap Voltage References
W. T. Holman
University of Arizona, Tucson, AZ
holman@ece.arizona.edu
W3E02
A5802
1481_jramirez4
High Speed IDDQ Current Sensors for VLSI System Testing
J. Ramirez-Angulo and G. Gonzalez-Altamirano
New Mexico State University, Las Cruces, NM
jramirez@nmsu.edu
W3E03
A5803
1251_harjani
A Low Voltage Class AB CMOS Amplifier
F. Wang, R. Heineke and R. Harjani
University of Minnesota, MN
harjani@ee.umn.edu
W3E04
A5804
0050_f80003
Measuring the Threshold Voltage of a MOSFET with an Active Attenuator
J.H. Tsay, S.I. Liu and Y.P. Wu
National Taiwan University, Taipei, TAIWAN, ROC
f80003@cctwin.ee.ntu.edu.tw
Wednesday, 1:30 p.m. -- 3:00 p.m., Room F
W3F00
Session Title: Digital Signal Processing -- A/D and D/A Conversion
Chair: R. Bamberger
Washington State University, Pullman, WA
bamberg@eecs.wsu.edu
W3F01
A4801
0108_ppvnath3
Optimum Pre- and Post Filters for Quantization
J. Tuqan and P.P. Vaidyanathan
California Institute of Technology, Pasadena, CA
ppvnath@sys.caltech.edu
W3F02
A4802
0313_chd
FPGA Based Systolic Array Architectures for Computing the
Discrete Fourier Transform
C. Dick La Trobe University, Melbourne, AUSTRALIA
chd@ee.latrobe.edu.au
W3F03
A4803
0597_tonydavies1
Periodic Non-linear Oscillation from Band-Pass Sigma-Delta Modulators
A. Davies
University of London, London, UK
tonydavies@bay.cc.kcl.ac.uk
W3F04
A4804
1291_chrenb
Delta-Sigma Demodulator With Large Oversampling Ratio Using the
One-Hot Residue Number System
W. Chren
NASA Lewis Research Center/Grand Valley State University, Grand Rapids, MI
chrenb@gvsu.edu
Wednesday, 1:30 p.m. -- 3:00 p.m., Room G
W3G00
Session Title: VLSI Systems and Applications -- Smart Interfaces for Sensors I
Chair: F. Maloberti
University of Pavia, Pavia, ITALY
franco@ipvsp4.unipv.it
W3G01
A6801
2501
A generic capacitive interface for smart sensors
N. Yazdi, A. Mason, K. Najafi and K.D. Wise
University of Michigan, Ann Arbor, MI
franco@ipvsp4.unipv.it
navid@engin.umich.edu
najafi@engin.umich.edu
W3G02
A6802
2502
Digital interface circuits using sigma-delta modulation for the
integrated micro-fluxgate
S. Kawahito, A. Yamasawa and K. Y. Tadokoro
Toyohasi University of Technology, Toyohashi, JAPAN
franco@ipvsp4.unipv.it
kawahito@tutics.tut.ac.jp
W3G03
A6803
2503
Offset-reduction in current-mode microsystems
J.H. Huigsing and A. Bakker
Technical University of Delft, Delft, NETHERLANDS
franco@ipvsp4.unipv.it
anton@et.tudelft.nl
W3G04
A6804
2504
An ultrasound source based on a micromachined electromechanical resonator
Qiuting Huang and Christoph Kuratli
ETH, Zurich, SWITZERLAND
franco@ipvsp4.unipv.it
huang@iis.ee.ethz.ch
Wednesday, 1:30 p.m. -- 3:00 p.m., Room H
W3H00
Session Title: Visual Signal Processing -- Image Processing I
Chair: Ya-Qin Zhang
David Sarnoff Research Center, Princeton, NJ
W3H01
A3801
1380_linares
JPEG Estimated Spectrum Adaptive Postfilter Using Image Adaptive
Q-Tables and Canny Edge Detectors
I. Linares, R.M. Mersereau and M.J.T. Smith
Georgia Institute of Technology, Atlanta, GA
linares@ee.gatech.edu
linares@gsfc.nasa.gov
W3H02
A3802
0276_zurbach
Weighted Myriad Filters for Image Processing
P. Zurbach, J.G. Gonzalez and G.R. Arce
University of Delaware, Newark, DE
pete_zurbach@smtp.svl.trw.com
W3H03
A3803
0928_mitras2
A Simple Method for the Restoration on Images Corrupted By Streaks
E. Abreu and S.K. Mitra
University of California, Santa Barbara, CA
mitra@ece.ucsb.edu
W3H04
A3804
1040_eeyau
A Multicoset Sampling Approach to the Missing Cone Problem in
Computer-Aided Tomography
P. Feng, S.F. Yau and Y. Bresler
University of Illinois at Urbana-Champaign, Urbana, IL
p-feng@csl.uiuc.edu
Wednesday, 1:30 p.m. -- 3:00 p.m., Room N, Poster Sessions
W3N00
Session Title: Analog Signal Processing -- Switched Circuit Applications
Chair: Antonio Petraglia
Federal University of Rio De Janeiro, RJ, BRAZIL
antonio@coe.ufrj.br
W3N01
A1811
0902_antonio
Recursive Switched-Capacitor Filters Having Approximately
Linear Phase Characteristics
A. Petraglia
Federal University of Rio De Janeiro, RJ, BRAZIL
antonio@coe.ufrj.br
W3N02
A1812
0429_paulo
Switched-capacitor Bandpass Decimator for High-frequency Narrowband
Channel Filtering and Downconversion
P. Santos and J.E. Franca
IST Center for Microsystems, Lisbon, PORTUGAL
paulo@ecsm4.ist.utl.pt
W3N03
A1813
0552_song
A Circuit Design of a Geometric-Mean Generator Based on the
Switched-Current Technique
M. Song
Samsung Electronics Co., Ltd. , KOREA
jkong@semigw.semi.samsung.co.kr
W3N04
A1814
0004_zeng
Total Charge Injection Cancellation Scheme for High Precision
Second Generation Switched-Current Circuits
X. Zeng, C. K. Tse and P. S. Tang
Hong Kong Polytechnic University, HONG KONG
zeng@encserver.en.polyu.edu.hk
W3N05
A1815
0532_thk2
A Novel Offset Current Cancellation Technique for Switched-Current
Circuits and Systems
K. Chen, T. Kuo and S. Lee
National Cheng Kung University Taiwan, TAIWAN, ROC
thk@sparc20.ee.ncku.edu.tw
W3N06
A1816
1222_p.shah
A New High-Speed Low Distortion Switched-Current Cell
P. Shah
Imperial College, London, UK
p.shah@ic.ac.uk
W3N06a
Session Title: Digital Signal Processing -- DSP Implementation III
Chair: J. Mellott
University of Florida, Gainesville, FL
jon@alpha.ee.ufl.edu
W3N07
A2811
0558_lemonds
A High Throughput 16 by 16 bit Multiplier for DSP Cores
C. Lemonds
Texas Instruments, Dallas, TX
lemonds@hc.ti.com
W3N08
A2812
0853_clwang
Systolic Array Implementation of Euclid's Algorithm for Inversion
and Division in GF(2^m)
J.-H. Guo and C.-L. Wang
National Tsing Hua University, Hsinchu, TAIWAN, ROC
clwang@ee.nthu.edu.tw
W3N09
A2813
0854_clwang2
A New Systolic Architecture for Fast DCT Computation
Y.-T. Chang, C.-L. Wang and C.-H. Chang
National Tsing Hua University, Hsinchu, TAIWAN, ROC
clwang@ee.nthu.edu.tw
W3N10
A2815
0593_hu_m
Implementation of One Bit Delay 2-D IIR Digital Filters
Z. Hu, G. King and D. Al-Dabass
Southampton Institute, Southampton, UK
hu_m@solent.ac.uk
W3N11
A2816
0865_jramirez3
Low-Voltage High-Frequency Continuous-Time Filters using Simple
OTAs and Gain-Stage Miller Integrations
J. Ramirez-Angulo and G. Gonzalez-Altamirano
New Mexico State University, Las Cruces, NM
jramirez@nmsu.edu
W3N11a
Session Title: Visual Signal Processing -- VLSI for Video Coding
Chair: Nicolas Demassieux, Telecom ENST, Paris, FRANCE
W3N12
A3811
1186_eezhong_frac
VLSI Architecture for Real-Time Fractal Video Encoding
Z. L. He, M. L. Liou and K. W. Fu
The Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, HONG KONG
eezhong@ee.ust.hk
W3N13
A3812
0112_przemek3
An Improved Architecture for the Adaptive Discrete Cosine Transform
F. Martin and D.R. Bull
University of Bristol, Bristol, UK
Dave.Bull@Bristol.ac.uk
W3N14
A3813
0968_chiperdf
Novel Systolic Array Design for Discrete Cosine Transform
with High Throughput Rate
D.-F. Chiper
Technical University Gh. Asachi, Iasi, ROMANIA
chiper@tuiasi.ro
W3N15
A3814
0115_rhpark2
A Novel VLSI Architecture for the Full Search Block Matching
Algorithm Using Systolic Array
S. B. Pan, S. S. Chae and R.-H. Park
Sogang University, Seoul, KOREA
rhpark@ccs.sogang.ac.kr
W3N16
A3815
0560_eezeng
An Enhanced Three Step Search Motion Estimation Method and its
VLSI Architecture
P. Lakamsani, M.L. Liou and B. Zeng
Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, HONG KONG
eezeng@ee.ust.hk
W3N17
A3816
1399_ms
Synthesis of Domain-Specific Heterogeneous Multiprocessor Systems:
Hybrid Video Coding Schemes - A Case Study
M. Schobinger and L. Thiele
Siemens AG, Munich, GERMANY
Swiss Federal Institute of Technology, Zurich, SWITZERLAND
ms@mess3.zfe.siemens.de
W3N17a
Session Title: Digital Signal Processing -- Parameter Estimation
Chair: M. Gabbouj
Tampere University of Technology, Pori, Finland
gabbouj@pori.tut.fi
W3N18
A4811
0565_dic
Fast SVD-Based Algorithm for Signal Selective DOA Estimation
G. Di Mario, E.D. Di Claudio and G. Orlandi
INFOCOM, Rome, ITALY
dic@infocom.ing.uniroma1.it
W3N19
A4812
0696_ycliang
A Efficient Parametric Approach to Joint Estimation of TDOA/FDOA
Using Higher Order Statistics
Y.-C. Liang and B.-H. Soong
Tsinghua University, Beijing, CHINA
Nanyang Technological University, SINGAPORE
bhlyc@tsinghua.edu.cn
W3N20
A4813
0284_kogon
Harmonic Long-Memory Signal Models
S.M. Kogon and D.G. Manolakis
Georgia Institute of Technology, Atlanta, GA
Boston College, Chestnut Hill, MA
kogon@eedsp.gatech.edu
W3N21
A4814
0425_samdi2
On Estimating ARMA Model Orders
A. Al-Smadi and D.M. Wilkes
Tennessee State University, Nashville, TN
Vanderbilt University, Nashville, TN
smadi@vuse.vanderbilt.edu
W3N22
A4815
1195_kozek
Matched Multiwindow Methods for the Estimation and Filtering of
Nonstationary Processes
W. Kozek, H. Feichtinger and J. Scharinger
University Vienna, AUSTRIA University Linz, AUSTRIA
kozek@tyche.mat.univie.ac.at
W3N23
A4816
1369_hli_sunysb_ee
An Iterative Procedure for Joint Bayesian Spectrum and Parameter
Estimation of Harmonic Signals
H. T. Li and P. M. Djuric
State University of New York at Stony Brook, NY
hli@sbee.sunysb.edu
W3N23a
Session Title: Analog Signal Processing -- Sampled Data Circuits and Systems
Chair: Andrea Baschirotto
University of Pavia, Pavia, ITALY
andrea@ipvsm6.unipv.it
W3N24
A5811
0555_tang
A 10-bit 100 MSamples/s BiCMOS D/A Converter
I.H.H. Jorgensen and S.A.T. Tunheim
Technical University of Denmark, Lyngby, DENMARK
SINTEF, Oslo, NORWAY
ihhj@ei.dtu.dk
W3N25
A5812
0571_barnettr
A 200MHz Differential Sampled Data FIR Filter for Disk Drive Equalization
R. Barnett and R. Harjani
VTC Inc., Bloomington, MN
University of Minnesota, Minneapolis, MN
barnettr@vtc.com
W3N26
A5813
0857_andrea
Design Considerations for a 10.7MHz BiCMOS high-Q Double-Sampled
SC Bandpass Filter
A. Baschirotto, A. Nagari, F. Montecchi and R. Castello
University of Pavia, Pavia, ITALY
SGS-Thomson, Agrate Brianza, ITALY
ANDREA@IPVSM6.UNIPV.IT
W3N27
A5814
0927_mitras
A New MIxed Analog-Digital Architecture for High Frequency Narrow
Band Channel Digitzation
R. Neves, A. Petraglia, S.K. Mitra and J.E. France
University of California, Santa Barbara, CA
Federal University of Rio de Janeiro, BRAZIL
Instituto Superior Tecnico, Lisbon, PORTUGAL
mitra@ece.ucsb.edu
rneves@ecsm4.ist.utl.pt
W3N28
A5815
1061_hjensen
A Hardware-Efficient Dynamic Element Matching D/A Converter Architecture
I. Galton and H.T. Jensen
University of California, Irvine, CA
galton@ece.uci.edu
W3N29
A5816
0040_dthelen
A 16 Bit 50 kHz ADC for Low Earth Orbit
D.C. Thelen
NASA Space Engineering Research Center for VLSI System Design
University of New Mexico, Albuquerque, NM
dthelen@groucho.mrc.unm.edu
W3N30
A6811
0691_sheumh
A Pipelined VLSI with Module Structure Design for
Discrete Wavelet Transforms
M.-H. Sheu, S.-F. Cheng and M.-D. Shieh
National Yunlin Institute of Technology, Yunlin, TAIWAN, ROC
sheumh@cad.el.yuntech.edu.tw
W3N31
A6812
0782_sunwoo
A Parallel Image Processor Chip for Real-Time Applications
M.H. Sunwoo, S. Ong, H. Chang and S. Ryu
Ajou University, Suwon, KOREA
sunwoo@madang.ajou.ac.kr
W3N32
A6813
0840_joujm
An On Line Adaptive Data Compression Chip using Arithmetic Codes
J.M. Jou, S. R. Kuang, Y.L. Chen and C.Y. Chiang
National Cheng Kung University, Taiwan, TAIWAN, ROC
jou@cad8.cme.ncku.edu.tw
W3N33
A6814
0951_mjamali
Module Generation Based VLSI Implementation of a Demultiplexer
for Satellite Communications
M.M. Jamali, S.C. Kwatra, D.H. Shetty and A.G. Eldin
University of Toledo, Toledo, OH
mjamali@uoft02.utoledo.edu
W3N34
A6815
1143_tim
A VLSI Implementation of the Continuous Wavelet Transform
R. T. Edwards and G. Cauwenberghs
Johns Hopkins University, Baltimore, MD
tim@bach.ece.jhu.edu
W3N35
A6816
1471_tokunbo2
High-Level Synthesis of a Digital Signal Processor Chip
F. Werner and T. Ogunfunmi
Santa Clara University, Santa Clara, CA
tokunbo@matthew.scu.edu
W3N35a
Session Title: Neural Systems and Applications -- Cellular Neural Networks
Chair: Angel Rodriguez-Vazquez
Centro Entro Nacional De Microelectronica,
Universidad De Sevilla, Sevilla, SPAIN
angel@cnm.us.es
W3N36
A7811
0272_apa
About the Robustness of CNN Linear Templates with Bipolar Images
A. Paasio, K. Halonen, V. Porra and A. Dawidziuk
Helsinki University of Technology, Espoo, FINLAND
Warsaw University of Technology, Warsaw, POLAND
apa@clara.hut.fi
W3N37
A7812
1176_eebert
Gabor-type Image Filtering with Cellular Neural Networks
B. E. Shi
Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, HONG KONG
eebert@ee.ust.hk
W3N38
A7813
0591_wang
On stability of CNN with non-symmetric opposite-sign templates
and non-unity gain output function
J. Wang, Q. Gan and Y. Wei
Southeast University, Nanjing, PR CHINA
wang@lmbe.seu.edu.cn
qgan@seu.edu.cn
W3N39
A7814
1403_brzakovic
Cellular Neural Network for Automatic Multilevel Halftoning of Digital Images
P.R. Bakic, N.S. Vujovic, D.P. Brzakovic and B.D. Reljin
Lehigh University, Bethlehem, PA
University of Belgrade, Belgrade, YUGOSLAVIA
db09@lehigh.edu
W3N40
A7815
1071_jtaylor
Large Neighbourhood Template Implementation in Continuous-time
Cellular Neural Networks with Physical Connectivity of r = 1
R. Akbari-Dilmaghani and J. Taylor
University College, London, UK
j.taylor@eleceng.ucl.ac.uk
W3N41
A7816
1353_numata
Design of Universal Pipelining Discrete Time Cellular Neural
Network by PARTHENON
H. Numata and M.Tanaka
Sophia University, Tokyo, JAPAN
tanaka@uranus.ee.sophia.ac.jp
W3N42
A8811
0707_eeccwai
An Improved Strategy with Transistor Re-Sizing Capability for
Converting Bulk CMOS Polygon Layout to SOI
M.C.W. Chow and P.C.H. Chan
Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, HONG KONG
eeccwai@ee.ust.hk
W3N43
A8812
1030_charvat
Pin Assignment for High-Performance MCM Systems
C. Harvatis, Y. Tekmen, G. Bilbro and P. Franzon
North Carolina State University, Raleigh, NC
charvat@eos.ncsu.edu
W3N44
A8813
1069_josepv
An Efficient Algorithm for Optimal Pairing and Chaining in Layout Generation
A.J. Velasco, Ll.Ribas, J.Riera, R.Peset Llopis and J.Carrabina
Universitat Autonoma de Barcelona, Bellaterra, SPAIN
josepv@cnm.es
W3N45
A8814
1204_sharon_hu_wmu
Efficient Algorithms for Orthogonal Polygon Approximation
D.Z. Chen, X. Hu and P.J. Blatner
University of Notre Dame, Notre Dame, IN
Western Michigan University, Kalamazoo, MI
IBM, Chicago, IL
sharon.hu@wmich.edu
W3N46
A8815
1268_aga
Very High Speed Circuit Layout Design with Automated Parasitic Symmetrization
D. Martin and A. Konczykowska
France Telecom - CNET, Laboratoire de Bagneux, Bagneux, FRANCE
aga@bagneux.cnet.fr
W3N47
A8816
1393_jhshao
A Seamless Parallel Algorithm for Full Chip Compaction
J.H. Shao and R.M.M. Chen
City University of Hong Kong, HONG KONG
jhshao@cpeelgx03.cityu.edu.hk
W3N48
1558
Static Timing Analyzer with Source/Drain Identification by Non-Z Procedure
K. Kuribayashi
kuribaya@dad.eec.toshiba.co.jp
W3N49
1321_meker
A Proposal for a Current Mode Wideband RF Amplifier Employing the Existing BJT Technology
M.M. Eker, S. Burgess, C. Lee and J. Choma
University of S. California, Los Angeles, CA
johnc@mizar.usc.edu
Wednesday, 3:30 p.m. - 5:00 p.m., Room A
W4A00
Session Title: Analog Signal Processing -- Delta-Sigma Delta Techniques II
Chair: Jiri Vlach
University of Waterloo, Waterloo, ON, CANADA
jvlach@vlsi.uwaterloo.ca
W4A01
A1901
0766_jvlach
RF to Digital Direct Conversion Architecture by Using PLL and
Sigma/Delta Modulatos Possibilities and Problems
L. Zhu, F. Chen and J. Vlach
University of Waterloo, Waterloo, ON, CANADA
jvlach@vlsi.uwaterloo.ca
W4A02
A1902
1129_sli
A Differential 25Mbit/s Switched-Current Delta-Sigma Modulator
S. Lindfors and K. Halonen
Helsinki University of Technology , Helsinki, FINLAND
sli@clara.hut.fi
W4A03
A1903
0377_motamed
Spectral Characteristics of the Double Loop Sigma Delta Modulator
with Unstable Filter Dynamics
M. Motamed, A. Zakhor and S. Sanders
University of California, Berkeley, CA
avz@eecs.berkeley.edu
W4A04
A1904
0525_acoban
A New Fourth-Order Single-Loop Delta-Sigma Modulator for Audio Applications
A. Coban and P. Allen
Georgia Institute of Technology, Atlanta, GA
acoban@monique.adgrp.gatech.edu
Wednesday, 3:30 p.m. - 5:00 p.m., Room B
W4B00
Session Title: Neural Systems and Applications -- Applications of Artificial
Neural Networks
Chair: Robert Newcomb, University of Maryland
W4B01
A7904
0582_liu
A Temporal Neural Network for the Noise Subspace of the Array Signal
R.-W. Liu and G. Dong
University of Notre Dame, Notre Dame, IN
liu.1@nd.edu
W4B02
A7902
2707
Synchronization of neural-type cells
A. Hodge, M. Zaghloul and R. W. Newcomb
University of Maryland, College Park, MD
George Washington University, Washington, DC
hodgeam@eng.umd.edu
zaghloul@seas.gwu.edu
newcomb@eng.umd.edu
W4B03
A7903
2703
Visual representation of the speech trace using neural networks
Pedro Gomez-Vilda, Victoria Rodellar-Biarge and Agustom Alvarez-Marqua
Universidad Politecnica, Madrid, SPAIN
pedro@pino.datsi.fi.upm.es
victoria@pino.datsi.fi.upm.es
newcomb@eng.umd.edu
W4B04
A7901
2706
Nonlinear projection to submanifolds using neural networks with
application to nonlinear data reduction
F. Salam, G. erten and H. Oh
Michigan State University, East Lansing, MI
IC Tech, Inc., Okemos, MI
newcomb@eng.umd.edu
salam@ee.msu.edu
oh@egr.msu.edu
ictech@mcimail.com
Wednesday, 3:30 p.m. - 5:00 p.m., Room C
W4C00
Session Title: Computer-Aided Design -- Symbolic Analysis Techniques
for Analog ICs
Chairs: M. M. Hassoun and Larry Huelsman
Iowa State University, Ames, IA
University of Arizona, Tuscon, AZ
marwan@iastate.edu
huelsman@ece.arizona.edu
W4C01
A8901
1901
Symbolic Analysis Tools - The State-Of-The-Art
Francisco V. Fernandez and Angel Rodriguez-Vzquez
Centro Nacional de Microelectronica, Sevilla, SPAIN
pacov@cnm.us.es
W4C02
A8902
1902
High-Level Data Conversion Synthesis by Symbolic Methods
Nuno C. Horta and Jose E. Franca
New University of Lisbon, PORTUGAL
franca@ecsm4.ist.utl.pt
W4C03
A8903
1904
A Family of Matroid Intersection Algorithms for the Computation
of Approximated Symbolic Network Functions
Piet Wambacq, Francisco Fernandez, Georges Gielen, Willy Sansen
and Angel Rodriguez-Vazquez
Katholieke Universiteit Leuven, Heverlee, BELGIUM
Piet.Wambacq@esat.kuleuven.ac.be
W4C04
A8904
1906
A Symbolic approach to the Fault Location in Analog Circuits
A. Luchetta, S. Manetti, G. Fedi and M.C. Piccirilli
Universita della Basilicata, Potenza, ITALY
Universita di Firenze, Firenze, ITALY
manetti@ingfi1.ing.unifi.it
luchetta@unibas.it
Wednesday, 3:30 p.m. - 5:00 p.m., Room D
W4D00
Session Title: Digital Signal Processing -- Filtering and Filter Design IV
Chair: I. Hartimo
Helsinki University of Technology, Helsinki, Finland
Iiro.Hartimo@hut.fi
W4D01
A2901
0229_hanna4
Velocity filters for multiple signal extraction by multiple
coherent interference attenuation in sensor array data
M.T. Hanna
University of Bahrain, Isa Town, BAHRAIN
eh049@cc.uob.bh
W4D02
A2902
0670_pbauer
Robust Stability of Linear Time-Varying Delta-Operator Formulated
Discrete-Time Systems
A.P. Molchanov and P.H. Bauer
Institute of Control Sciences, Moscow, RUSSIA
University of Notre Dame, Notre Dame, IN
pbauer@mars.ee.nd.edu
W4D03
A2903
0967_dabrow
Information Extraction from 1-D and 2-D Signals using Wavelet Transform
A. Dabrowski
Poznan Univ of Technology, Poznan, POLAND
dabrow@et.put.poznan.pl
W4D04
1562
Feature Enhancement From Nonlinear Time Series Using Linear-Phase
and Nonlinear-Phase Time-Delay Fuzzy Combiners
D. Campbell and L. Cahill
La Trobe University, Bundoora, Victoria, AUSTRALIA
D.Campbell@ee.latrobe.edu.au
Wednesday, 3:30 p.m. - 5:00 p.m., Room E
W4E00
Session Title: Analog Signal Processing -- Analog Nonlinear Circuits
Chair: Jose Silva-Martinez
Instituto Nacional de Astrofisica Optica y Electronica, Puebla, Pue, MEXICO
jsilva@tonali.inaoep.mx
W4E01
A5901
1307_jsilva_voltlim
Adjustable CMOS Voltage Limiter for Low-Voltage Applications
J. Silva-Martinez
Instituto Nacional de Astrofisica Optica y Electronica, Puebla, Pue, MEXICO
jsilva@tonali.inaoep.mx
W4E02
A5902
1097_mandell
Current-Mode Piecewise-Linear Function Generator
M. Delgado-Restituto, J. Ceballos-Caceres and A. Rodriguez-Vazquez
Centro Nacional de Microelectronica, Sevilla, SPAIN
mandel@cnm.us.es
W4E03
A5903
1378_frances
A Low Power Logarithmic A/D Converter
F. Francesconi and F. Maloberti
University of Pavia, Pavia, ITALY
frances@ipvsp4.unipv.it
W4E04
A7714
0645_furst
A Low-Noise/Low-Power Preamplifier for Capacitive Microphones
C.E. Furst
Technical University of Denmark, Lyngby, DENMARK
furst@ei.dtu.dk
Wednesday, 3:30 p.m. - 5:00 p.m., Room F
W4F00
Session Title: Digital Signal Processing -- M-D CAS and Signal Processing II
Chair: H. C. Reddy
California State University, Long Beach, CA
hreddy@engr.csulb.edu
W4F01
A4901
3002
A survey of new immittance-type stability tests for two-dimensional
digital filters
Y. Bistritz
DSP Group
ybistritz@dspgroup.dspg.com
hreddy@eng.uci.edu
W4F02
A4902
3003
Model reduction of multidimensional systems
P. Dewilde
Technical University of Delft, Delft, NETHERLANDS
dewilde@dimes.tudelft.nl
hreddy@eng.uci.edu
W4F03
A4903
3004
Recent results in model reduction methods for 2-D discrete systems
W. -S. Lu, J. Lou, and A. Antoniou
University of Victoria, Victoria, CANADA
andreas@ece.uvic.ca
hreddy@eng.uci.edu
W4F04
A4904
3005
Low roundoff noise structures for 2-D filters
P. Agathoklis
University of Victoria, Victoria, CANADA
andreas@ece.uvic.ca
hreddy@eng.uci.edu
Wednesday, 3:30 p.m. - 5:00 p.m., Room G
W4G00
Session Title: VLSI Systems and Applications -- Smart Interfaces for Sensors II
Chair: F. Maloberti
University of Pavia, Pavia, ITALY
franco@ipvsp4.unipv.it
W4G01
A6901
2505
A MOSFET-only interface for integrated flow sensors
Qiuting Huang, Christain Menolfi and Clemens Hammerschmied
ETH, Zurich, SWITZERLAND
franco@ipvsp4.unipv.it
huang@iis.ee.ethz.ch
W4G02
A6902
2506
Sigma delta processing in multisensor systems for carbon monoxide detection
V. Liberali, F. Maloberti and D. Tonietto
University of Pavia, Pavia, ITALY
franco@ipvsp4.unipv.it
W4G03
A6903
2507
Smart interfaces for sensors
H. Baltes
ETH, Zurich, SWITZERLAND
franco@ipvsp4.unipv.it
W4G04
A6904
3201
A Programmable Smart CMOS Sensor for Real-Time Pattern
Classification Applications
H. Djahanshahi, G. A. Jullien and W. C. Miller
University of Windsor, Windsor, CANADA
jullien@engn.uwindsor.ca
Wednesday, 3:30 p.m. - 5:00 p.m., Room H
W4H00
Session Title: Visual Signal Processing -- Image Processing II
Chair: Mark Smith
Georgia Tech, Atlanta, GA
W4H01
A3901
0110_przemek1
Low Complexity Two-Dimensional Digital Filters using
Unconstrained SPT Term Allocation
S. Sriranganathan, D.R. Bull and D.W. Redmill
University of Bristol, Bristol, UK
Dave.Bull@Bristol.ac.uk
W4H02
A3902
1486_hinamo
2-D State-Space Digital Filters with Error Spectrum Shaping
T. Hinamoto, S. Karino and N. Kuroda
Hiroshima University, Higashi-Hiroshima, JAPAN
hinamoto@ecl.sys.hiroshima-u.ac.jp
W4H03
A3903
0636_lgchen
An Efficient Visual Pattern Block Truncation Coding
L.-G. Chen and Y.-C. Liu
National Taiwan University, Taipei, TAIWAN, ROC
lgchen@video.ee.ntu.edu.tw
W4H04
A3904
0762_corte
A Frequency Domain Technique for Estimating Rigid Planar Rotations
G.M. Cortelazzo, L. Lucchese and C. Monti
Electronical Information Department, Padova, ITALY
corte@dei.unipd.it
Wednesday, 3:30 p.m. - 5:00 p.m., Room N, Poster Sessions
W4N00
Session Title: Analog Signal Processing -- Basic Analog Building Blocks
Chair: Federico Montecchi
SGS-Thomson, Agrate Brianza, ITALY
W4N01
A1911
0203_harjani
A Non-Slewing Opamp for Oversampled Converters
R. Harjani
University of Minnesota, Minneapolis, MN
harjani@ee.umn.edu
W4N02
A1912
1098_manetakis
A new high-frequency very low output-impedance cmos buffer
K. Manetakis and C. Toumazou
Imperial College, London, UK
k.manetakis@ic.ac.uk
W4N03
A1913
0317_edmundp
Low-voltage Gilbert current-gain cell
E. Pierzchala, O. O'Shana, P. Van Halen, and M. A. Perkowski
Portland State University, Portland, OR and Analogix Corp.
edmundp@ee.pdx.edu
W4N04
A1914
0332_kimmo
Balanced Dynamically Biased Continuous-Time Current Integrator for
Low Power Low Distortion Signal Processing
K. Koli, K. Halonen and E. Tiiliharju
Helsinki University of Technology, Espoo, FINLAND
kimmo@clara.hut.fi
W4N05
A1915
0628_danilo2
Low Voltage Low Power CMOS Four-Quadrant Analog Multiplier for
Neural Network Applications
G. Colli and F. Montecchi
SGS-Thomson Microelectronics - Agrate B. (MI), ITALY
collig@stm.com
W4N06
A1916
1306_jsilva
Improving the High-Frequency Response of the Folded-Cascode Amplifiers
J. Silva-Martinez
Instituto Nacional de Astrofisica Optica y Electronica, Puebla, Pue, MEXICO
jsilva@tonali.inaoep.mx
W4N06a
Session Title: Digital Signal Processing -- Transform Analysis and
Computation
Chair: P. Kuosmanen
Tampere University of Technology, Tampere, FINLAND
pqo@cs.tut.fi
W4N07
A2911
0101_omair4
Vector Split-Radix Algorithm for DFT Computation
D. Sundararajan and M.O. Ahmad
Concordia University, Montreal, CANADA
omair@ece.concordia.ca
W4N08
A2912
0105_pei2
Discrete Fractional Fourier Transform
S. C. Pei and M. H. Yeh
National Taiwan University, Taipei, TAIWAN, ROC
pei@cc.ee.ntu.edu.tw
W4N09
A2913
0220_khasawneh2
Two-Dimensional Chirp Z-Transform and its Application to Zoom Wigner Bispectrum
J.A. Draidi, N.M. Ghuneimi and M.A. Khasawneh
Jordan University of Science & Technology, Irbid, JORDAN
mkha@amra.nic.gov.jo
W4N10
A2914
0681_elegargh
On Skew Circular Convolution Algorithms over Finite Integer Rings
H.K. Garg
National University of Singapore, SINGAPORE
elegargh@leonis.nus.sg
W4N11
A2915
1246_kozick
Parallel Recursive Algorithms for Inverse Discrete Legendre Transform
and Inverse Discrete Laguerre Transform
M. F. Aburdene, J. Zheng and R. J. Kozick
Bucknell University, Lewisburg, PA
kozick@bucknell.edu
W4N12
A2916
1343_timor_power
Analysis of Power Consumption in a Simple Embedded Data Path Unit
T. Rahkonen
University of Oulu, Oulu, FINLAND
timor@ee.oulu.fi
W4N12a
Session Title: Video Coding III
Chair: Weiping Li
Lehigh University, Bethlehem, PA
W4N13
A3911
0032_defasa
B-Spline filter banks for very low bit rate coding
S. de Faria and M. Ghanbari
University of Essex, Colchester, UK
defasa@essex.ac.uk
W4N14
A3912
0924_fuhuei
A Quality Measure Based Rate Control Strategy for MPEG Encoders
F.-H. Lin and R.M. Mersereau
Georgia Institute of Technology, Atlanta, GA
fuhuei,rmm@ee.gatech.edu
W4N15
A3913
0661_wcsiu
Efficient Interframe Transform Coding Using Temporal Context
Y.-L. Chan and W.-C. Siu
Hong Kong Polytechnic University, Hung Hom, HONG KONG
enwcsiu@hkpucc.polyu.edu.hk
W4N16
A3914
0772_weiku
The Arbitrarily Shaped Transform of Segmented Motion Field
for a Pseudo Object-Oriented Very Low Bit-Rate Video Coding System
C.-W. Ku, Y.-M. Chiu, L.-G. Chen and Y.-P. Lee
National Taiwan University, TAIWAN, ROC
william@video.ee.ntu.edu.tw
W4N17
A3915
1107_monaco
Video Coding Using Image Warping within Variable Size Blocks
J. Monaco and M. Smith
Georgia Institute of Technology, Atlanta, GA
monaco@ee.gatech.edu
W4N18
A3916
0194_bruton
3-D Model Based Coding - Very Low Bit Rate Coding Scheme for Video-conferencing
J. Provine and L. Bruton
University of Calgary, Alberta, CANADA
bruton@enel.ucalgary.ca
W4N18a
Session Title: Digital Signal Processing -- DSP for Communications
Chair: B. Stewart
University of Strathclyde, Glasgow, UK
bob@spd.eee.strath.ac.uk
W4N19
A4911
1188_hcso
A Generalized Equalization-Based Algorithm for Multipath Time Delay Estimation
H.C. So and P.C. Ching
The Chinese University of Hong Kong, HONG KONG
hcso@ee.cuhk.edu.hk
W4N20
A4912
1248_za3eem_parhi
Comparison of Discrete Multitone and Carrierless AM/PM Techniques
for Line Equalization
A. Shalash and K.K. Parhi
University of Minnesota, Minneapolis, MN
parhi@ee.umn.edu
W4N21
A4913
0686_lim
Pipelined FIR Filter Architecture and Increasing Performance of
Decision-Feedback Equalizer
I.-T. Lim
LG Electronics Research Center, Seoul, KOREA
lim@corvette.crl.goldstar.co.kr
W4N22
A4914
0336_vesma
Interpolation Filters with Arbitrary Frequency Response
for All-Digital Receivers
J. Vesma and T. Saramaki
Tampere University of Technology, Tampere, FINLAND
Jussi.Vesma@cs.tut.fi
W4N23
A4915
1342_timor_fm
A 3 V Fully Integrated Digital FM demodulator Based on a CMOS
Pulse-Shrinking Delay Line
T. Rahkonen, E. Malo and J. Kostamovaara
University of Oulu, Oulu, FINLAND
Nokia Mobile Phones, Oulu, FINLAND
timor@ee.oulu.fi
W4N24
A4916
1360_jeff
Frequency Estimation of Travelling Ionospheric Disturbances
J.M. O'Keefe, D.A. Campbell and L.W. Cahill
La Trobe University, Bundoora, Victoria, AUSTRALIA
jeff@ee.latrobe.edu.au
W4N24a
Session Title: Analog Signal Processing -- Analog Circuit Applications II
Chair: Terri Fiez
Washington State University, Pullman, WA
terri@eecs.wsu.edu
W4N25
A5911
0808_isc
A Very Low Level Optical Pulse Detection Receiver with High
Dynamic Range without AC Coupling
S. Narathong, C. Saunders and B. DeCaro
Irvine Sensors Co., Costa Mesa, CA
isc@cerf.net
W4N26
A5912
1124_seema
Analysis of Non-Idealities in Folding and Interpolating ADCs
using a Behavioral Model Approach
S. Varma, K. Suyama and V. Gopinathan
Columbia University, New York, NY
AT&T, Holmdel, NJ
seema@elab.columbia.edu
W4N27
A5913
1328_gert2
Adaptive Calibration of Multiple Quantization Oversampled A/D Converters
G. Cauwenberghs and G.C. Temes
Johns Hopkins University, Baltimore, MD
Oregon State University, Corvallis, OR
gert@jhunix.hcf.jhu.edu
W4N28
A5914
1330_terri3
A Comparison of Three Parallel Delta-Sigma A/D Converters
A. Eshraghi and T. Fiez
Washington State University, Pullman, WA
terri@eecs.wsu.edu
W4N29
A5915
0640_farrell
A Novel Approach to Bounding the Integrator Outputs of Second Order
Sigma-Delta Convertors
R.J. Farrell and O.C. Feely
University College, Dublin, IRELAND
rfarrell@ollamh.ucd.ie
W4N30
A5916
0347_igor
Low-Voltage Current Operational Amplifier with a Very Low Current Consumption
I. Mucha
Technical University of Denmark, Lyngby, DENMARK
igor@ei.dtu.dk
W4N31
A6911
0397_drechsle
Exact Minimization of Kronecker Expressions for Symmetric Functions
B. Becker and R. Drechsler
Albert-Ludwigs-University, Freiburg, GERMANY
drechsle@informatik.uni-freiburg.de
W4N32
A6912
0820_bogdan4
Composite Complex Hadamard Spectra of Boolean Functions
B.J. Falkowski and S. Rahardja
Nanyang Technological University, SINGAPORE
bogdan@ntu.ac.sg
W4N33
A6913
0873_bogdan5
Family of Fast Transforms for Mixed Arithmetic Logic
S. Rahardja and B.J. Falkowski
Nanyang Technological University, SINGAPORE
bogdan@ntu.ac.sg
W4N34
A6914
0598_bogdan
Operations on Boolean Functions and Variables in Spectral Domain
of Arithmetic Transform
C.H. Chang and B.J. Falkowski
Nanyang Technological University, SINGAPORE
bogdan@ntu.ac.sg
W4N35
A6915
1201_rgupta
Control Optimization using Timed Decision Tables
R. K. Gupta and J. Li
University of Illinois, Urbana, IL
rgupta@cs.uiuc.edu
W4N36
A6916
0213_chw
A Systolic RSA Public Key Cryptosystem
P.-S. Chen, S.-A. Hwang and C.-W. Wu
National Tsing Hua University, Hsinchu, TAIWAN, ROC
c.wu@ieee.org
W4N36a
Session Title: Neural Systems and Applications -- Applications IV
Chair: Jacek Zurada
University of Louisville, Louisville, KY
jmzura02@starbase.spd.louisville.edu
W4N37
A7911
1508_frank
The Generalized CMAC
F. Gonzalez-Serrano, A. Artes-Rodriguez and A. Vidal
Univ. of Vigo, Spain
frank@tsc.uvigo.es
W4N38
A7912
1166_murgu
Adaptive Control for ATM Traffic Smoothing Based on Receding
Horizon Mappings with Neural Networks
A. Murgu
University of Jyvaskyla, Jyvaskyla, FINLAND
murgu@julia.math.jyu.fi
W4N39
A7913
1132_soumitra
Temporal Pattern Learning in Noisy Recurrent Neural Networks
S. Das and O. Olurotimi
George Mason University Fairfax, VA
soumitra@bass.gmu.edu
W4N40
A7914
0731_tsui
An Adaptive Neural Network in Wavelet Space for Time-Series Prediction
F.-C. Tsui, C.C. Li, M. Sun and R.J. Sclabassi
University of Pittsburgh, Pittsburgh, PA
tsui@neuronet.pitt.edu
W4N41
A7915
0712_s.g.hu
The Performance Analysis of a New-Type Neural Network Code-Division
Multiple- Access Receiver
S.G. Hu, P. Zhang and J.D. Hu
Beijing University of Posts and Telecommunications, PR CHINA
jdhu@bupt.edu.cn
W4N42
A7916
0935_xibi
An Hypercomplex Neural Network Platform for Robot Positioning
L. Fortuna, G. Muscato and M.G. Xibilia
University of Catania, Catania, ITALY
xibi@dees.unict.it
W4N43
A8911
0614_moraes
Pre-Layout Performance Prediction for Automatic Macro-Cell Synthesis
F. Moraes, R. Reis, L. Torres, M. Robert and D. Augergne
Universidade Federal do Rio Grande do Sul, BRAZIL
Universite de Montpellier II, Lirmm, FRANCE
moraes@inf.ufrgs.br
W4N44
A8912
0693_shiehm
A CAD System for Automatic Synthesis of Generalized Asynchronous Circuits
M.-D. Shieh, J.-M. Horng and M.-H. Sheu
National Yunlin Institute of Technology, Yunlin, TAIWAN, ROC
shiehm@cad.el.yuntech.edu.tw
W4N45
A8913
0781_ckn
A New Strategy of Performance-Directed Technology Mapping Algorithm
for LUT-Based FPGAs
K.N. Chen, T.S. Wang and Y.T. Lai
National Cheng Kung University, Taiwan, TAIWAN, ROC
ckn@cad8.cme.ncku.edu.tw
W4N46
A8914
1123_saab
Identifying Redundancies Using Reduced Symbolic Simulation
B. Mathew and D.G. Saab
Case Western Reserve University, Cleveland, OH
MIPS Technologies, Inc., Mountain View, CA
saab@alpha.cwru.edu
W4N47
A8915
1149_uchida
Generating a Hierarchical Simulation Model on the Basis of Functional
Model of Register Transfers
T. Uchida, H. Kiya, and A. Yamada
Tokyo Metropolitan University, Tokyo, JAPAN
uchida@isys.eei.metro-u.ac.jp
W4N48 -- TO BE PRESENTED IN PLACE OF M3N13
A8916
1469_hoisko
Specification, Hardware Implementation and Prototyping Environment
for Image Processing Algorithms
S. Hoisko, H. Hakkarainen, K. Vihavainen and J. Isoaho
Tampere University of Technology, Tampere, FINLAND
hoisko@cs.tut.fi
W4N49
0680_wada
A Flexible Design of Nonuniformly Oversampled Multirate Filter Banks
S. Wada, H. Yagi and T. Saito
Tokyo Denki University, Saitama, JAPAN
wada@j.dendai.ac.jp
W4N50
1345_kxiong_hmc
Stability Analysis of Nonliinear Neural Network Models
K. Xiong
The Claremont Graduate School Claremont, CA
xiongk@cgs.edu
[]