Homework_3 -- Using the Spartan3 Demo Board
The original PASS test file is at /usr/cad/course/spartan3/pass.mcs
HowToBurnSerialProm
Slides (restricted pdf)
................. 
Spartan3 User Guide (64-page pdf)
Part B -- Using Xilinx ISE Software
If you wish to install the free PC version of the Xilinx WebPack tools on your own PC,
access WebPack.
Please note that filenames and paths should not include any spaces when using the Xilinx software.
Open ISE and from the menu select and download "Help-->Tutorials-->ISE Quick Start".
Follow the ISE Quick Start Tutorial to implement a VHDL counter.
To view the layout following place/route, in the Processes tab, expand "place & route" and
double-click the "View Routed Design (FPGA Editor)" process.
Use "screen-print" and "Paint" to capture the graphic.
Download the design to the Spartan3 Demo Board.
Part C -- Synthesizing and Downloading Your Own Design
Now, synthesize a VHDL source file that contains a BCD counter with UP/DOWN control.
Upon power-up, the counter should be initially ZERO and its value displayed on the
right-most digit, dig<0>. When btn0 is pressed (properly), the slide switch, swt<0>,
should be read to determine whether to count UP (swt = '1') or DOWN (swt = '0').
The counter should change once per second. The other digits should be BLANK.
Change the display refresh rate from 10Hz to a faster value.
Like the IRS that does random audits, some of you will be asked to demonstrate
the working design on the Spartan3 Demo Board but all should be prepared to do so.
Grab your own post-layout simulation and floorplan (layout) for each part of hw3.
Link them and your VHDL source file and the stim file to your restricted website.
Edit /usr/cad/public_html/551hw_status.html to reflect the status of your homework.
Update /usr/cad/public_html/551hw_status.html
dbouldin@tennessee.edu