Homework 5 -- Graphics <---> HDL
Design Entry and Control
HDL2Graphics:
Read the following tutorial and note the capabilites of the tool:
hds_hdl2graphics.pdf (42 pages)
Seq_Generator.vhd
uut_top_block_p17
control_state_diagram_p22
control_flow_diagram_p25
statecad
statecad-flow
generated_schematic
Graphics2HDL:
Read the following tutorial and note the capabilites of the tool:
hds_graphics2hdl.pdf (254 pages)
tut_top_block_p33
tut_state_diagram_p38
tut_truth_table_p70
GUI Tutorial:
Execute this tutorial on any machine except vlsi6
(fpgadvpro is our alias for fa_with_ls)
and capture a block diagram, a flowchart, a breakpoint
simulation waveform and a schematic:
Fpgadv tutorial (38 pages pdf).
mkdir hw5
cd hw5
mentor_tools
fpgadvpro &
/sw/mentor/fpgadv61/Hds/examples/tutorial_ref/Import
Select either the Verilog or the VHDL example.
ModelSim Commands (2-page pdf)
ModelSim User Guide (752-page pdf)
ModelSim Tutorial (152-page pdf)
Student Workbook on Leonardo Synthesis (1.6 MByte pdf file)
Student Workbook Source Code (tar file)
Link your results to your restricted webpage.
Edit /usr/cad/public_html/551hw_status.html to reflect the status of your homework.
Update /usr/cad/public_html/551hw_status.html
dbouldin@tennessee.edu