Homework_3 -- Designing an 8-bit Adder Datapath
Note: For Fall 2006, you do not have to implement this homework. Just view the tutorial.
Follow the USC Cadence Tutorial (html)
or (pdf)
to draw schematics and symbols
(which may be rectangles) to implement a full adder as a single-bit slice.
To save time, you may copy some of the schematics from the
OSU/IIT Library.
Layout the single-bit adder using the datapath library rules discussed in class.
Array the single-bit adder into an 8-bit datapath.
Simulate the design for the single-bit and 8-bit implementations using Verilog-XL
(pre-layout only) and SPECTRE (both pre-layout and post-layout).
Set all eight A inputs to 1 and all eight B inputs to 0.
Then, apply the following to the Carry-in input on the LSB:
tran1 tran start=0 stop=20n step=0.05n errpreset=moderate
Measure the delay between the mid-point on the LSB Carry-in input
to the mid-point on the MSB Carry-out output as shown
here.
Students whose last name begins with A-J, use:
nfets with W/L = 10/2 (lambda) = 2.0/0.4
pfets with W/L = 24/2 (lambda) = 4.8/0.4
The remaining students can use identical W/Ls for the pfets and nfets:
nfets with W/L = 10/2 (lambda) = 2.0/0.4
pfets with W/L = 10/2 (lambda) = 2.0/0.4
The topology that I suggest for Homework 3 can be used by all:
| XOR | NAND/NOR | XOR | INV/NAND/NAND |
| | | | |
| p-n | n - p | p-n | n-p |
| | n - p | | n-p |
| | | | n-p |
| | | | |
Vdd GND Vdd GND Vdd
For the I/O, let Ai and Bi enter from the left on poly and SUMi exit
on the right on metal-2. The carry signals should align perfectly in
the vertical dimension as well as the Vdd and GND buses. You should have
room to also let the Carry-in enter each bit-slice on the left in poly and
the Carry-out exit on the right in metal-2. Only the LSB Carry-in and the
MSB Carry-out need to be connected externally when you simulate the 8-bit adder.
Adam's Solutions
Robert Greenwell's Solutions (restricted)
Link your results to your web home page.
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dbouldin@tennessee.edu