Homework_4 -- Loading Effects and Sizing Transistors
Note the latest Spice results.
Using the INVX1 and FAX1 from the OSU-AMI-06 library,
construct a 4-bit adder (as the DUT) and add shaping inputs and loads.
Replace "inh_inh_bn" with "vdd!" for the ami06P fets and "0" for the ami06N fets.
Draw the schematic,
simulate pre-layout using Verilog-XL and Spectre,
perform the single-row layout,
drc, extraction, lvs and simulate post-layout using Spectre.
Be sure to extract parasitic capacitance.
Connect two INVX1 cells in series to shape the Carry-in of the LSB slice.
Connect two INVX1 cells in series to the MSB-Sum. Repeat this for the MSB-Carry-Out.
All of the A inputs of the 4-bit adder should be connected to Vdd and
all of the B inputs of the 4-bit adder should be connected to GND.
The other three sets of outputs of the 4-bit adder should be left unconnected.
Note these errors and workarounds from Fall 2005.
Make connections between cells with metal-1 or metal-2.
Do not add any capacitors on any output nodes since the INVX1 cells add just what is needed.
For the Spectre simulation, apply the following to the input of the shaping INVX1 chain of the LSB Carry-in input:
Be sure to include add_si.inp with no Cout)
Vin (Cin 0) vsource type=pwl wave=[0n 0 5n 0 5.5n 5 8n 5 8.5n 0 20n 0]
tran1 tran start=0 stop=20n step=0.05n errpreset=moderate
Measure the delay for each case (except case-7) from the mid-point of the LSB Carry-in adder input
to the mid-point of the MSB Carry-out adder output.
For case-7, measure the delay from the mid-point of the LSB Carry-in adder input
to the mid-point of the BUFX4-output.
Make a table of your post-layout delays and plot Delay vs. #loads.
CASE:
(1) 4-bit adder with no load
(2) 4-bit adder with 1 load-chain
(3) 4-bit adder with 4 load-chains
(4) 4-bit adder with 8 load-chains
(5) 4-bit adder with 1 load-chain interconnected with 1000-micron metal-1 wire (1.2-microns wide)
(6) 4-bit adder with 1 load interconnected with 1000-micron poly wire (1.2-microns wide)
(7) 4-bit adder followed by BUFX4 with 8 load-chains
(8) 4-bit adder with larger internal W's in the MSB-slice to achieve the same delay as case 7.
(Just copy case 4 to be case 8 and edit the W's to have the same delay as case 7.)
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Discuss your results for each case. Note that case-5 should be slower than case-2 and case-6
should be even slower. Please record your situation since some students have obtained results
contrary to this, indicating that we have an error in our tech file.
Link your results to your web home page.
Update /usr/cad/public_html/651hw_status.html
dbouldin@tennessee.edu