MICROELECTRONIC SYSTEMS RESEARCH LABORATORY

UNIVERSITY OF TENNESSEE, KNOXVILLE

DESIGN FLOW OF AREA-ARRAY INTEGRATED CIRCUIT

1. Chip Core Design

2. Template of the Area-Array Padframe

3. Padframe with top 2 metal layers of the core

4. Area-Array Padframe (Pitch I)

5. Final Area-Array IC (Pitch I)

6. Area-Array Padframe (Pitch II)

7. Final Area-Array IC (Pitch II)

8. Another Area-Array Padframe (Pitch III)

9. Final Area-Array IC (Pitch III)

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