The development of a system-on-chip (SoC) is an ongoing project in the Electrical & Computer Engineering Department at the University of Tennessee. Led by Prof. Don Bouldin, a group of graduate students has assembled a CPU, RAM and various IP (intellectual property) blocks into a single design. The design has been simulated with ModelSim (both pre-synthesis and post-layout), synthesized with Synopsys Design Compiler and physically implemented using the Cadence First Encounter and Silicon Ensemble place/route packages.
Initially the design used only "open" or freely available components as described in Ref. 1 below. During 2005, built-in self-test and repair circuits have been added with the help of tools and IP from DAFCA, a startup company located in suburban Boston. Thus, instrumentation has been inserted into the SoC to verify the chip in-silicon and at-speed. In some cases, the circuitry not only detects errors but can perform workarounds to restore proper operation. Ref. 2 describes these enhancements which are also outlined in these slides (0.6 MByte pdf file).
We intend to fabricate the design on a 180-nanometer process during Fall 2005.
[1] Bouldin, D. and R. Srivastava, ``An Open System-on-Chip Platform for Education'' (0.5 MByte pdf file) , Proceedings of 2004 European Workshop on Microelectronics Education (EWME), Lausanne, Switzerland, April 15-16, 2004.
[2] Jiang, W., T. Marwah and D. Bouldin, ``Enhancing Reliability and Flexibility of a System-on-Chip Using Reconfigurable Logic'' (0.2 MByte pdf file) , Proceedings of the Midwest Symposium on Circuits and Systems (MWSCAS), Cincinnati, OH, Aug. 7-10, 2005.