SYNTHESIS OF FPGAS AND TESTABLE ASICS
Prof. Don Bouldin
Electrical Engineering
University of Tennessee
Knoxville, TN 37996-2100
dbouldin@utk.edu
ABSTRACT
Industrial designers and educators who plan to design microelec
tronic systems (e.g. hardware accelerators, co-processors, etc.)
are increasingly capturing their designs using hardware
description languages such as VHDL and Verilog. The designs are
then most often synthesized into programmable logic devices such
as field-programmable gate arrays (FPGAs) offerred by Xilinx,
Altera, Actel and others. This approach places the emphasis on
high-level design which reduces time to market by relying
on synthesis software and programmable logic to produce working
prototypes rapidly. These prototypes may then be altered as
requirements change or converted into high-volume mask gate
arrays or other application-specific integrated circuits (ASICs)
when the demand is known to be sufficient. These ASICs,
however, must be designed to be testable to screen out those with
manufacturing defects. Hence, scan logic must be inserted, test
vectors generated and fault grading performed to ensure a high
level of testability. These efforts complicate and delay the
conversion of FPGA designs to ASICs but must be considered by
designers of microelectronic sytems.
2-Page Overview (postscript file from MSE-97)
11-Page Narrative (postscript file from VLSI-97)
Microelectronic System Courses at Univ. of Tennessee
dbouldin@utk.edu